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PDF RTL8201CP Data sheet ( Hoja de datos )
| Número de pieza | RTL8201CP | |
| Descripción | SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER | |
| Fabricantes | REALTEK | |
| Logotipo |  |
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RTL8201CP
SINGLE-CHIP/SINGLE-PORT
10/100M FAST ETHERNET PHYCEIVER
(With Auto Crossover)
DATASHEET
Rev. 1.21
12 October 2004
Track ID: JATR-1076-21
1 page  
RTL8201CP
Datasheet
Table 24. UTP Mode and SNI Interface......................................................................................................17
Table 25. Fiber Mode and MII Interface .....................................................................................................17
Table 26. Auto-Negotiation Mode Pin Settings ..........................................................................................18
Table 27. LED Definitions ..........................................................................................................................19
Table 28. Power Saving Mode Pin Settings ................................................................................................20
Table 29. Absolute Maximum Ratings........................................................................................................23
Table 30. Operating Conditions...................................................................................................................23
Table 31. Power Dissipation........................................................................................................................23
Table 32. Input Voltage: Vcc.......................................................................................................................23
Table 33. MII Transmission Cycle Timing .................................................................................................24
Table 34. MII Reception Cycle Timing.......................................................................................................25
www.DataShTeaebt4lUe.c3o5m. SNI Transmission Cycle Timing .................................................................................................27
Table 36. SNI Reception Cycle Timing ......................................................................................................28
Table 37. MDC/MDIO Timing....................................................................................................................29
Table 38. Crystal Characteristics.................................................................................................................30
Table 39. Transformer Characteristics ........................................................................................................30
Table 40. Ordering Information...................................................................................................................33
List of Figures
Figure 1. Block Diagram .............................................................................................................................2
Figure 2. Pin Assignments...........................................................................................................................3
Figure 3. Read Cycle .................................................................................................................................15
Figure 4. Write Cycle ................................................................................................................................15
Figure 5. LED and PHY Address Configuration.......................................................................................19
Figure 7. MII Transmission Cycle Timing-1.............................................................................................24
Figure 8. MII Transmission Cycle Timing-2.............................................................................................25
Figure 9. MII Reception Cycle Timing-1 ..................................................................................................26
Figure 10. MII Reception Cycle Timing-2 ..................................................................................................26
Figure 11. SNI Transmission Cycle Timing-1 ............................................................................................27
Figure 12. SNI Transmission Cycle Timing-2 ............................................................................................27
Figure 13. SNI Reception Cycle Timing-1..................................................................................................28
Figure 14. SNI Reception Cycle Timing-2..................................................................................................28
Figure 15. MDC/MDIO Timing ..................................................................................................................29
Figure 16. MDC/MDIO MAC to PHY Transmission Without Collision ...................................................29
Figure 17. MDC/MDIO PHY to MAC Reception Without Error ...............................................................30
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
v
Track ID: JATR-1076-21 Rev. 1.21
5 Page 
RTL8201CP
Datasheet
5.5. Device Configuration Interface
Name
Type
ISOLATE
I
RPTR
SPEED
I
LI
www.DataSheet4DUU.coPmLEX
ANE
LI
LI
LDPS
I
MII/SNIB LI/O
Pin No.
43
40
39
38
37
41
44
Table 5. Device Configuration Interface
Description
Set high to isolate the RTL8201CP from the MAC. This will also isolate the MDC/MDIO
management interface. In this mode, the power consumption is minimum. This pin can be
directly connected to GND or VCC.
Set high to put the RTL8201CP into repeater mode. This pin can be directly connected
to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to put
the RTL8201CP into 100Mbps operation. This pin can be directly connected to GND or
VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable full duplex. This pin can be directly connected to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable Auto-negotiation mode, set low to force mode. This pin can be directly
connected to GND or VCC.
Set high to put the RTL8201CP into LDPS mode. This pin can be directly connected
to GND or VCC. See 7.7 Power Down, Link Down, Power Saving, and Isolation
Modes, page 20, for more information.
This pin is latched to input during a power on or reset condition. Pull high to set
the RTL8201CP into MII mode operation. Set low for SNI mode. This pin can be
directly connected to GND or VCC.
5.6. LED Interface/PHY Address Configuration
These five pins are latched into the RTL8201CP during power up reset to configure the PHY address
[0:4] used for the MII management register interface. In normal operation, after initial reset, they are used
as driving pins for status indicator LEDs. The driving polarity, active low or active high, is determined by
each latched status of the PHY address [4:0] during power-up reset. If the latched status is High, then it
will be active low. If the latched status is Low, then it will be active high. See section 7.5 LED and PHY
Address Configuration, page 19, for more information.
Name
PHYAD0/
LED0
PHYAD1/
LED1
PHYAD2/
LED2
Type
LI/O
LI/O
LI/O
Table 6. LED Interface/PHY Address Configuration
Pin No. Description
9 PHY Address [0].
Link LED.
Lit when linked.
10 PHY Address [1].
Full Duplex LED.
Lit when in Full Duplex operation.
12 PHY Address [2].
CP LED Mode: 10 ACT LED
Blinking when transmitting or receiving data.
BL LED Mode: Link 10 / ACT LED
Active when linked in 10Base-T mode, and blinking when transmitting or
receiving data.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
6
Track ID: JATR-1076-21 Rev. 1.21
11 Page | ||
| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet RTL8201CP.PDF ] | |
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