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PDF P2S28D40CTP Data sheet ( Hoja de datos )
| Número de pieza | P2S28D40CTP | |
| Descripción | (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM | |
| Fabricantes | MIRA | |
| Logotipo |  |
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Deutron Electronics Corp.
P2S28D30/40CTP
128M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x
16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals
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are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and
output data and data strobe are referenced on both edges of CLK. The P2S28D30/40CTP achieves
very high speed clock rate up to 200 MHz .
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture ; two data transfers per clock cycle.
- Bidirectional , data strobe (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- Commands entered on each positive CLK edge ;
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0 , BA1 (Bank Address)
- /CAS latency –2.0 / 2.5/ 3 (programmable) ;
Burst length - 2 / 4 / 8 (programmable)
Burst type - Sequential / Interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles / 64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-11 / Column address A0-9 , A0-9(x8) /A0-8(x16)
- SSTL_2 Interface
- Package
400-mil, 66-pin Thin Small Outline Package (TSOP II)
with 0.65mm lead pitch
- JEDEC standard for -6 , -75
- Intel standard for -5
DDR SDRAM (Rev.1.0)
Deutron Electronics Corp.
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Deutron Electronics Corp.
P2S28D30/40CTP
128M Double Data Rate Synchronous DRAM
BLOCK DIAGRAM
P2S12D40ATP
DLL
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DQ0 - 15
I/O Buffer
UDQS,LDQS
DQS Buffer
Memory
Array
Bank #0
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
A0-11 BA0,1
Clock Buffer
Control Signal Buffer
/CS /RAS /CAS /WE UDM,
CLK /CLK CKE
LDM
Type Designation Code
P 2 S 28 D 4 0 C TP –G5
This rule is applied to only Synchronous DRAM family.
G: Lead Free
Speed Grade 75: 133MHz @CL=2.5, and 100MHz @CL=2.0
6: 167MHz @CL=2.5, and 133MHz @CL=2.0
5: 200MHz @CL=3.0, 167MHz @CL=2.5, and 133MHz @CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2 n 2: x4, 3: x8, 4: x16
DDR Synchronous DRAM
Density 28: 128M bits
Interface S:SSTL_3, _2
Memory Style (DRAM)
MIRA DRAM
DDR SDRAM (Rev.1.0)
Deutron Electronics Corp.
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Deutron Electronics Corp.
P2S28D30/40CTP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
REFRESHING H X X X X
DESEL
L H H HX
NOP
L H H L BA
TERM
L H L X BA, CA, A10 READ / WRITE
L L H H BA, RA
ACT
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L L H L BA, A10
PRE / PREA
L L L HX
REFA
LL
Op-Code, Mode-
LL
MRS
Add
MODE
HX
REGISTER L H
SETTING L H
X XX
H HX
H L BA
DESEL
NOP
TERM
L H L X BA, CA, A10 READ / WRITE
L L H H BA, RA
ACT
L L H L BA, A10
PRE / PREA
L L L HX
REFA
LL
Op-Code, Mode-
L L Add
MRS
Action
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Row Active after tRSC)
NOP (Row Active after tRSC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
DDR SDRAM (Rev.1.0)
Deutron Electronics Corp.
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