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PDF 28F010 Data sheet ( Hoja de datos )
| Número de pieza | 28F010 | |
| Descripción | Search ----- CAT28F010 | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28F010
1 Megabit CMOS Flash Memory
Licensed Intel second source
FEATURES
I Fast read access time: 90/120 ns
I Low power CMOS dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
www.DataSheet4IU.cHomigh speed programming:
–10 µs per byte
–2 Sec Typ Chip Program
I 0.5 seconds typical chip-erase
I 12.0V ± 5% programming and erase voltage
I Stop timer for program/erase
ALOGEN FR
LEA D F REETM
I Commercial, industrial and automotive
temperature ranges
I On-chip address and data latches
I JEDEC standard pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP (8 x 20)
I 100,000 program/erase cycles
I 10 year data retention
I Electronic signature
DESCRIPTION
The CAT28F010 is a high speed 128K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and EEPROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F010 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
BLOCK DIAGRAM
I/O0–I/O7
ERASE VOLTAGE
SWITCH
I/O BUFFERS
WE COMMAND
REGISTER
CE
OE
A0–A16
VOLTAGE VERIFY
SWITCH
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
Y-DECODER
X-DECODER
Y-GATING
1,048,576 BIT
MEMORY
ARRAY
1
Doc. No. 1019, Rev. D
1 page  
CAT28F010
SUPPLY CHARACTERISTICS
Symbol
Parameter
VCC
VPPL
VPPH
VCC Supply Voltage
VPP During Read Operations
VPP During Read/Erase/Program
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified.
Limits
Min Max.
4.5 5.5
0 6.5
11.4 12.6
www.DataSheet4U.com
JEDEC Standard
28F010-90(7)
Symbol Symbol Parameter
Min Max
tAVAV
tELQV
tRC Read Cycle Time
tCE CE Access Time
90
90
tAVQV
tGLQV
tAXQX
tGLQX
tELZX
tGHQZ
tEHQZ
tWHGL(1)
tACC
tOE
tOH
tOLZ(1)(6)
tLZ(1)(6)
tDF(1)(2)
tDF(1)(2)
-
Address Access Time
OE Access Time
Output Hold from Address OE/CE Change
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
Write Recovery Time Before Read
0
0
0
6
90
35
20
30
28F010-12(7)
Min
120
0
0
0
6
Max
120
120
50
30
40
Unit
V
V
V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Testing Load Circuit (example)
1.3V
5108 FHD F03
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
5 Doc. No. 1019, Rev. D
5 Page 
CAT28F010
Erase Mode
During the first Write cycle, the command 20H is written
into the command register. In order to commence the
erase operation, the identical command of 20H has to be
written again into the register. This two-step process
ensures against accidental erasure of the memory con-
tents. The final erase cycle will be stopped at the rising
edge of WE, at which time the Erase Verify command
(A0H) is sent to the command register. During this cycle,
the address to be verified is sent to the address bus and
latched when WE goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci-
www.DataSheet4fUic.acotimon. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
& STANDBY
COMMAND
& DATA
PROGRAM
VERIFY
PROGRAMMING COMMAND
PROGRAM VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAS tAH
CE (E)
tCS
tCH
tCH
tCS
tCH
OE (G)
tGHWL
tWPH
tWHWH1
tWHGL
WE (W)
DATA (I/O)
tWP
tDS
HIGH-Z
DATA IN
= 40H
tDH
tDS
tWP
DATA IN
tDH
VCC 5.0V
0V
VPP VPPH
VPPL
tVPEL
tWP
tDS
tDH
DATA IN
= C0H
tOE
tOLZ
tLZ
tCE
tRC
tEHQZ
tDF
tOH
VALID
DATA OUT
28F010 F08
11 Doc. No. 1019, Rev. D
11 Page | ||
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| PDF Descargar | [ Datasheet 28F010.PDF ] | |
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