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PDF SSTV16857 Data sheet ( Hoja de datos )
| Número de pieza | SSTV16857 | |
| Descripción | 14-Bit Register | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 2000
Revised June 2005
www.DataSheet4U.com
SSTV16857 • SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
applications. The SSTVN16857 is a 14-bit register
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Features
s Compliant with DDR-I registered module specifications
s Operates at 2.5V r 0.2V VDD
s SSTL-2 compatible input and output structure
s Differential SSTL-2 compatible clock inputs
s Low power mode when device is reset
s Industry standard 48 pin TSSOP package
Ordering Code:
Order Number Package Number
Package Description
SSTV16857MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
SSTVN16857MTD
(Preliminary)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Q1-Q14
D1-D14
RESET
CK
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
VREF
VDDQ
VDD
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Truth Table
RESET
Dn
CK
L X or X or
Floating Floating
HLn
HHn
HX L
HXH
L Logic LOW
H Logic HIGH
X Don’t Care, but not floating unless noted
n LOW-to-HIGH Clock Transition
p HIGH-to-LOW Clock Transition
CK
X or
Floating
p
p
H
L
Qn
L
L
H
Qn
Qn
© 2005 Fairchild Semiconductor Corporation DS500387
www.fairchildsemi.com
1 page  
www.DataSheet4U.com
AC Electrical Characteristics (SSTV16857) (Note 4)
Symbol
Parameter
fMAX
Maximum Clock Frequency
tW
tACT
(Note 5)
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
data inputs must be LOW after RESET HIGH (Figure 3)
tINACT
(Note 5)
Differential Inputs De-activation Time,
data and clock inputs must be held at valid levels
(not floating) after RESET LOW
tS Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5)
Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
tH Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5)
Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
tREM
tPHL, tPLH
Reset Removal Time (Figure 7)
Propagation Delay CLK, CLK to Qn (Figure 4)
tPHL Propagation Delay RESET to Qn (Figure 6)
tSK(Pn-Pn) Output to Output Skew
Note 4: Refer to Figure 1 through Figure 7.
Note 5: This parameter is not production tested.
Note 6: For data signal input slew rate t 1 V/ns.
Note 7: For data signal input slew rate t 0.5 V/ns and 1 V/ns.
Note 8: For CK, CK signals input slew rates are t 1 V/ns.
TA 0qC to 70qC, CL 30 pF, RL 50:
VDD 2.5V r 0.2V; VDDQ 2.5V r 0.2V
Min Max
200
2.5
22
22
0.65
0.9
0.75
0.9
10
1.1
2.8
5.0
200
AC Electrical Characteristics (SSTVN16857) (Note 9)
Symbol
Parameter
fMAX
Maximum Clock Frequency
tW
tACT
(Note 5)
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
data inputs must be LOW after RESET HIGH (Figure 3)
tINACT
(Note 5)
Differential Inputs De-activation Time,
Data and Clock Inputs must be held at valid levels
(not floating) after RESET LOW
tS Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5)
Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
tH Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5)
Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
tREM
tPHL, tPLH
tPSS
Reset Removal Time (Figure 7)
Propagation Delay CLK, CLK to Qn (Figure 4)
Propagation Delay Simultaneous Switching CLK, CLK to Qn (Note 14)
tPHL Propagation Delay RESET to Qn (Figure 6)
tSK(Pn-Pn) Output to Output Skew
Note 9: Refer to Figure 1 through Figure 7.
Note 10: This parameter is not production tested.
Note 11: For data signal input slew rate t 1 V/ns.
Note 12: For data signal input slew rate t 0.5 V/ns and 1 V/ns.
Note 13: For CK, CK signals input slew rates are t 1 V/ns.
Note 14: Simultaneous Switching is guaranteed by characterization.
TA 0qC to 70qC, CL 30 pF, RL 50:
VDD 2.5V r 0.2V; VDDQ 2.5V r 0.2V
Min Max
220
2.5
22
22
0.65
0.75
0.75
0.9
10
1.1
2.4
2.7
5.0
200
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ps
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet SSTV16857.PDF ] | |
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