PDF ASM5I9352 Data sheet ( Hoja de datos )

Número de pieza	ASM5I9352
Descripción	11-Output Zero Delay Buffer
Fabricantes	Alliance Semiconductor
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No Preview Available ! July 2005 rev 0.2 ASM5I9352 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Features Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz www.DataSheet4U.com2.5V or 3.3V operation Split 2.5V/3.3V outputs ± 2% max Output duty cycle variation 11 Clock outputs: Drive up to 22 clock lines LVCMOS reference clock input 125-pS max output-output skew PLL bypass mode Spread AwareTM Output enable/disable Pin compatible with MPC9352 and MPC952 Industrial temperature range: –40°C to +85°C 32-Pin 1.0mm TQFP & LQFP Packages The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:22. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 16.67 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. Functional Description The ASM5I9352 is a low voltage high performance 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications. When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. 1 page July 2005 ASM5I9352 rev 0.2 DC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) Parameter Description Condition Min Typ Max Unit VIL Input Voltage, Low LVCMOS 0.7 V VIH Input Voltage, High VOL Output Voltage, Low1 VOH Output Voltage, High1 LVCMOS IOL= 15 mA IOH= –15 mA 1.7 VDD+ 0.3 V 0.6 V 1.8 V IIL Input Current, Low IIH Input Current, High2 VIL= VSS VIL= VDD –10 µA 100 µA IDDA www.DataSheet4U.com IDDQ PLL Supply Current Quiescent Supply Current AVDD only All VDD pins except AVDD 5 10 mA 3 5 mA IDD Dynamic Supply Current 170 mA CIN Input Pin Capacitance 4 pF ZOUT Output Impedance 17 – 20 Ω Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission lines. 2.Inputs have pull-down resistors that affect the input current. DC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C) Parameter Description Condition Min Typ Max Unit VIL Input Voltage, Low LVCMOS 0.8 V VIH Input Voltage, High LVCMOS 2.0 VDD + 0.3 V VOL Output Voltage, Low1 IOL= 24 mA IOL= 12 mA 0.55 V 0.30 VOH Output Voltage, High1 IOH= –24 mA 2.4 V IIL Input Current, Low IIH Input Current, High2 VIL= VSS VIL= VDD –10 µA 100 µA IDDA PLL Supply Current AVDD only 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 3 5 mA IDD Dynamic Supply Current 240 mA CIN Input Pin Capacitance 4 pF ZOUT Output Impedance 14 – 17 Ω Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission lines. 2.Inputs have pull-down resistors that affect the input current. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 12 5 Page July 2005 rev 0.2 ASM5I9352 Ordering Information Part Number ASM5I9352-32-ET ASM5I9352-32-LT ASM5I9352G-32-ET ASM5I9352G-32-LT Marking ASM5I9352 ASM5I9352 ASM5I9352G ASM5I9352G Package Type 32-pin TQFP 32-pin LQFP –Tape and Reel 32-pin TQFP, Green 32-pin LQFP –Tape and Reel, Green Temperature Industrial Industrial Industrial Industrial www.DataSheetD4Ue.vcoicme Ordering Information ASM 5I9352 F-32-LT R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 12 11 Page

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