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PDF IT8700F Data sheet ( Hoja de datos )

Número de pieza IT8700F
Descripción Simple LPC I/o
Fabricantes Integrated Technology Express　
Logotipo Integrated Technology Express Logotipo



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IT8700F
Simple Low Pin Count Input / Output (Simple LPC I/O)
Preliminary Specification V0.1

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IT8700F pdf
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Contents
CONTENTS
1. Features ...................................................................................................................................................1
2. General Description..................................................................................................................................3
3. Block Diagram ..........................................................................................................................................5
4. Pin Configuration ......................................................................................................................................7
5. IT8700F Pin Descriptions........................................................................................................................ 11
6. List of GPIO Pins .................................................................................................................................... 21
7. Power On Strapping Options .................................................................................................................. 25
8. Configuration .......................................................................................................................................... 27
8.1 Configuring Sequence Description ............................................................................................ 27
8.2 Description of the Configuration Registers................................................................................. 28
8.2.1 Logical Device Base Address ........................................................................................... 34
8.3 Global Configuration Registers (LDN: All) ................................................................................. 35
8.3.1 Configure Control (Index=02h) ......................................................................................... 35
8.3.2 Logical Device Number (LDN, Index=07h)........................................................................ 35
8.3.3 Chip ID Byte 1 (Index=20h, Default=87h) ......................................................................... 35
8.3.4 Chip ID Byte 2 (Index=21h, Default=05h) ......................................................................... 35
8.3.5 Configuration Select and Chip Version (Index=22h, Default=02h)..................................... 35
8.3.6 Software Suspend (Index=23h, Default=00h) ................................................................... 35
8.3.7 Clock Selection and Flash ROM I/F Control Register (Index=24h, Default=sssss000b) ..... 36
8.3.8 GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=00h) .................... 36
8.3.9 GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h) .................... 37
8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h) .................... 37
8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=FFh).................... 38
8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=E0h).................... 39
8.3.13 GPIO Set 6 Multi-Function Pin Selection Register (Index=2Ah, Default=FFh) ................... 40
8.3.14 Test Mode Register 1 (Index=2Eh, Default=00h) .............................................................. 40
8.3.15 Test Mode Register 2 (Index=2Fh, Default=00h) .............................................................. 40
8.4 FDC Configuration Registers (LDN=00h) .................................................................................. 41
8.4.1 FDC Activate (Index=30h, Default=00h) ........................................................................... 41
8.4.2 FDC Base Address MSB Register (Index=60h, Default=03h)............................................ 41
8.4.3 FDC Base Address LSB Register (Index=61h, Default=F0h) ............................................ 41
8.4.4 FDC Interrupt Level Select (Index=70h, Default=06h)....................................................... 41
8.4.5 FDC DMA Channel Select (Index=74h, Default=02h) ....................................................... 41
8.4.6 FDC Special Configuration Register 1 (Index=F0h, Default=00h)...................................... 42
8.4.7 FDC Special Configuration Register 2 (Index=F1h, Default=00h)...................................... 42
8.5 Serial Port 1 Configuration Registers (LDN=01h) ...................................................................... 42
8.5.1 Serial Port 1 Activate (Index=30h, Default=00h) ............................................................... 42
8.5.2 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) ................................. 42
8.5.3 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h) .................................. 43
8.5.4 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h)........................................... 43
8.5.5 Serial Port 1 Special Configuration Register (Index=F0h, Default=00h)............................. 43
8.6 Serial Port 2 Configuration Registers (LDN=02h) ...................................................................... 43
8.6.1 Serial Port 2 Activate (Index=30h, Default=00h) ............................................................... 43
8.6.2 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) ................................. 43
8.6.3 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h) ................................ 44
8.6.4 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) ........................................... 44
8.6.5 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h) .......................... 44
8.6.6 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)........................... 44
8.6.7 Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h).......................... 45
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IT8700F V0.1

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IT8700F arduino
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Contents
Table 6-3. General Purpose I/O Group 3...................................................................................................... 22
Table 6-4. General Purpose I/O Group 4...................................................................................................... 22
Table 6-5. General Purpose I/O Group 5...................................................................................................... 22
Table 6-6. General Purpose I/O Group 6Note ................................................................................................. 23
Table 6-7. Programming of Pins 82, 83, 84, and 85...................................................................................... 23
Table 7-1. Power On Strapping Options ....................................................................................................... 25
Table 8-1. Global Configuration Registers .................................................................................................... 28
Table 8-2. FDC Configuration Registers ....................................................................................................... 29
Table 8-3. Serial Port 1 Configuration Registers ........................................................................................... 29
Table 8-4. Serial Port 2 Configuration Registers ........................................................................................... 29
Table 8-5. Parallel Port Configuration Registers ........................................................................................... 30
Table 8-6. FAN Controller Configuration Registers ....................................................................................... 30
Table 8-7. GPIO Configuration Registers ..................................................................................................... 31
Table 8-8. Game Port Configuration Registers ............................................................................................. 32
Table 8-9. Consumer IR Configuration Registers.......................................................................................... 33
Table 8-10. MIDI Port Configuration Registers ............................................................................................. 33
Table 8-11. Base Address of Logical Devices............................................................................................... 34
Table 9-1. Address Map on the ISA Bus....................................................................................................... 65
Table 9-2. FAN Controller Registers............................................................................................................. 66
Table 9-3. Digital Output Register (DOR) ..................................................................................................... 73
Table 9-4. Tape Drive Register (TDR).......................................................................................................... 73
Table 9-5. Main Status Register (MSR) ........................................................................................................ 74
Table 9-6. Data Rate Select Register (DSR) ................................................................................................ 75
Table 9-7. Data Register (FIFO)................................................................................................................... 75
Table 9-8. Digital Input Register (DIR).......................................................................................................... 76
Table 9-9. Diskette Control Register (DCR).................................................................................................. 76
Table 9-10. Status Register 0 (ST0) ............................................................................................................. 77
Table 9-11. Status Register 1 (ST1) ............................................................................................................. 78
Table 9-12. Status Register 2 (ST2) ............................................................................................................. 79
Table 9-13. Status Register 3 (ST3) ............................................................................................................. 79
Table 9-14. Command Set Symbol Descriptions........................................................................................... 80
Table 9-15. Command Set Summary ........................................................................................................... 82
Table 9-16. Effects of MT and N Bits............................................................................................................ 90
Table 9-17. SCAN Command Result............................................................................................................ 92
Table 9-18. VERIFY Command Result ......................................................................................................... 93
Table 9-19. Interrupt Identification................................................................................................................ 95
Table 9-20. HUT Values (ms)....................................................................................................................... 95
Table 9-21. SRT Values (ms)....................................................................................................................... 96
Table 9-22. HLT Values ............................................................................................................................... 96
Table 9-23. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands......................... 96
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