DS1672 Datasheet PDF - Dallas Semiconductor
Part Number | DS1672 | |
Description | Low Voltage Serial Timekeeping Chip | |
Manufacturers | Dallas Semiconductor | |
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PRELIMINARY
DS1672
Low Voltage Serial Timekeeping Chip
FEATURES
32-bit counter
2-wire serial interface
Automatic power-fail detect and switch
circuitry
Power-fail reset output
Low-voltage oscillator operation (1.3V min.)
Trickle charge capability
ORDERING INFORMATION
DS1672X-X
2 2.0V operation
3 3.0V operation
33 3.3V operation
blank 8-pin DIP
S 8-pin SOIC
U 8-pin µSOP
PIN ASSIGNMENT
X1
X2
VBACKUP
GND
1
2
3
4
8 VCC
7 RST
6 SCL
5 SDA
PIN DESCRIPTION
VCC, VBACKUP
GND
- Power Supply Inputs
- Ground
X1, X2
- 32.768 kHz crystal pins
SCL - Serial clock
SDA
- Serial data
RST - Reset output
DESCRIPTION
The DS1672 incorporates a 32-bit counter and power monitoring functions. The 32-bit counter is
designed to count seconds and can be used to derive time of day, week, month, month, and year by using
a software algorithm. A precision temperature-compensated reference and comparator circuit monitors
the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated
which forces the reset to the active state. When VCC returns to an in-tolerance condition, the reset signal
is kept in the active state for 250 ms to allow the power supply and processor to stabilize.
OPERATION
The block diagram in Figure 1 shows the main elements of the DS1672. As shown, communications to
and from the DS1672 occur serially over a 2-wire bi-directional bus. The DS1672 operates as a slave
device on the serial bus. Access is obtained by implementing a START condition and providing a device
identification code followed by a register address. Subsequent registers can be accessed sequentially until
a STOP condition is executed.
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DS1672
2-WIRE SERIAL DATA BUS
The DS1672 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a “master." The devices that are controlled by the master are “slaves.” The
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1672 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see Figure 4).
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between the START and the STOP conditions is not limited, and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
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Information | Total 13 Pages | |
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Download | [ DS1672.PDF Datasheet ] |
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