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PDF 29F001TPC Data sheet ( Hoja de datos )
| Número de pieza | 29F001TPC | |
| Descripción | MX29F001TPC | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX29F001T/B
1M-BIT [128K x 8] CMOS FLASH MEMORY
FEATURES
• 5.0V ± 10% for read, erase and write operation
• 131072x8 only organization
• Fast access time: 90/120ns
• Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase (8K-Byte x 1, 4K-Byte x 2, 8K Byte
x 2, 32K-Byte x 1, and 64K-Byte x 1)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically programs and verifies data at
specified address
• Erase Suspend/Erase Resume
– Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation.
• Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
• Chip protect/unprotect for 5V only system or 5V/12V
system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 32-pin PLCC
- 32-pin TSOP
- 32-pin PDIP
• Boot Code Sector Architecture
- T=Top Boot Sector
- B=Bottom Boot Sector
• 20 years data retention
GENERAL DESCRIPTION
The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's
Flash memories offer the most cost-effective and
reliable read/write non-volatile random access
memory. The MX29F001T/B is packaged in 32-pin
PLCC, TSOP, PDIP. It is designed to be repro-
grammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F001T/B offers access time
90ns. To eliminate bus contention, the MX29F001T/
B has separate chip enable (CE) and output enable
(OE) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs
and fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The
MX29F001T/B uses a 5.0V ± 10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N: PM0515
REV. 2.6, DEC. 29, 2003
1
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MX29F001T/B
TABLE 1. SOFTWARE COMMAND DEFINITIONS
Command
First Bus
Bus Cycle
Cycle Addr Data
Second Bus
Cycle
Addr Data
Third Bus
Cycle
Addr Data
Fourth Bus
Cycle
Addr Data
Fifth Bus
Cycle
Sixth Bus
Cycle
Addr Data Addr Data
Reset
1 XXXH F0H
Read
1 RD RD
Read Silicon ID
4 555H AAH 2AAH 55H 555H 90H ADI DDI
Chip Protect Verify 4 555H AAH 2AAH 55H 555H 90H (SA) 00H
X02H 01H
Program
4 555H AAH 2AAH 55H 555H A0H PA PD
Chip Erase
6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Sector Erase
6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30H
Unlock for chip
6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H
protect/unprotect
Note:
1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to
Table 3)
DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A16 in either state.
4. For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data
is 00H, it means the chip is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register
command sequences. Note that the Erase Suspend
(B0H) and Erase Resume (30H) commands are valid
only while the Sector Erase operation is in progress.
Either of the two reset command sequences will reset
the device(when applicable).
P/N: PM0515
REV. 2.6, DEC. 29, 2003
5
5 Page 
www.DataSheet4U.com
MX29F001T/B
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not suc-
cessfully completed. Data Polling and Toggle Bit are the
only operating functions of the device under this condi-
tion.
If this time-out condition occurs during sector erase op-
eration, it is specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other sec-
tors. Write the Reset command sequence to the device,
and then execute program or erase command sequence.
This allows the system to continue to use the other ac-
tive sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector may not be re-
used, (other sectors are still functional and can be re-
used).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au-
tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept addi-
tional sector erase commands. To insure the command
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been accepted.
DATA PROTECTION
The MX29F001T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory con-
tents only occurs after successful completion of spe-
cific command sequences. The device also incorporates
several features to prevent inadvertent write cycles re-
sulting from VCC power-up and power-down transition or
system noise.
P/N: PM0515
REV. 2.6, DEC. 29, 2003
11
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