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A25L05P PDF Datasheet - AMIC Technology

Part Number A25L05P
Description (A25LxxP) Serial Flash Memory
Manufacturers AMIC Technology 
Logo AMIC Technology Logo 
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A25L05P datasheet, circuit
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A25L20P/A25L10P/A25L05P Series
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
Document Title
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No.
0.0
0.1
1.0
History
Initial issue
Add transient voltage (<20ns) on any pin to ground potential spec.
Final version release
Issue Date
February 13, 2007
April 24, 2007
August 9, 2007
Remark
Preliminary
Final
(August, 2007, Version 1.0)
AMIC Technology Corp.

1 page
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A25L05P pdf, schematic
A25L20P/A25L10P/A25L05P Series
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
FEATURES
„ 2Mbit / 1Mbit / 512Kbit of Flash Memory
„ Flexible Sector Architecture
- 25L20P: (4/4/8/16/32)KB/64x3 KB
- 25L10P: (4/4/8/16/32)KB/64x1KB
- 25L05P: (4/4/8/16/32)KB
„ Bulk Erase (typical)
- 25L20P (2M) in 6s
- A25L10P (1M) in 4s
- A25L05P (512K) in 3s
„ Sector Erase (512 Kbit) in 1s (typical)
„ Page Program (up to 256 Bytes) in 3ms (typical)
„ 2.7 to 3.6V Single Supply Voltage
„ SPI Bus Compatible Serial Interface
„ 85MHz Clock Rate (maximum)
„ Deep Power-down Mode 1µA (typical)
„ Top or Bottom boot block configuration available
„ Electronic Signatures
- JEDEC Standard Two-Byte Signature
A25L20P: (2012h, Bottom) or (2022h, top)
A25L10P: (2011h, Bottom) or (2021h, top)
A25L05P: (2010h, Bottom) or (2020h, top)
- RES Instruction, One-Byte, Signature, for backward
compatibility
A25L20P (11h)
A25L10P (10h)
A25L05P (05h)
„ Package options
- 8-pin SOP (150mil or 209mil), 8-pin DIP (300mil) or 8-pin
QFN
- All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25L20P/A25L10P/A25L05P are 2M/1M/512 bit Serial
Flash Memory, with advanced write protection mechanisms,
accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using
the Page Program instruction.
The memory is organized as 4/2/1 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole memory
can be viewed as consisting of 1024/512/256 pages, or 262,144
/131,072/65,536 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
Pin Configurations
„ SO8 Connections
„ DIP8 Connections
„ QFN8 Connections
A25L20P/
A25L10P/
A25L05P
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
A25L20P/
A25L10P/
A25L05P
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
A25L20P/
A25L10P/
A25L05P
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
(August, 2007, Version 1.0)
1 AMIC Technology Corp.

2 Page
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A25L05P equivalent
A25L20P/A25L10P/A25L05P Series
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
SDO
SDI
SCK
Bus Master
(ST6, ST7, ST9,
ST10, Other)
CS3 CS2 CS1
C DO DIO
SPI Memory
Device
S W HOLD
C DO DIO
C DO DIO
SPI Memory
Device
S W HOLD
SPI Memory
Device
S W HOLD
Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL CPHA
00
C
11
C
DIO
DO
MSB
MSB
(August, 2007, Version 1.0)
4 AMIC Technology Corp.

5 Page
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A25L05P diode, scr
A25L20P MEMORY ORGANIZATION
The memory is organized as:
„ 262,144 bytes (8 bits each)
„ 4 sectors (one (4/4/8/16/32) Kbytes & 64x3 Kbytes
„ 1024 pages (256 bytes each).
Table 2. Memory Organization
A25L20P Top Boot Block Address Table
Sector
3-4
Sector Size (Kbytes)
4
3-3 4
3-2 8
3-1 16
3-0 32
2 64
1 64
0 64
A25L20P Bottom Boot Block Address Table
Sector
Sector Size (Kbytes)
3 64
2 64
1 64
0-4 32
0-3 16
0-2 8
0-1 4
0-0 4
A25L20P/A25L10P/A25L05P Series
Each page can be individually programmed (bits are
programmed from 1 to 0). The device is Sector or Bulk
Erasable (bits are erased from 0 to 1) but not Page Erasable.
3F000h
3E000h
3C000h
38000h
30000h
20000h
10000h
00000h
Address Range
3FFFFh
3EFFFh
3DFFFh
3BFFFh
37FFFh
2FFFFh
1FFFFh
0FFFFh
30000h
20000h
10000h
08000h
04000h
02000h
01000h
00000h
Address Range
3FFFFh
2FFFFh
1FFFFh
0FFFFh
07FFFh
03FFFh
01FFFh
00FFFh
(August, 2007, Version 1.0)
8 AMIC Technology Corp.

9 Page
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A25L05P transistor, igbt
Page Program (PP)
The Page Program (PP) instruction allows bytes to be
programmed in the memory (changing bits from 1 to 0).
Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip
Select ( S ) Low, followed by the instruction code, three
address bytes and at least one data byte on Serial Data Input
(DIO). If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the
same page (from the address whose 8 least significant bits
(A7-A0) are all zero). Chip Select ( S ) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 12. If more than
256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be
A25L20P/A25L10P/A25L05P Series
programmed correctly within the same page. If less than 256
Data bytes are sent to device, they are correctly programmed
at the requested addresses without having any effects on the
other bytes of the same page.
Chip Select ( S ) must be driven High after the eighth bit of the
last data byte has been latched in, otherwise the Page
Program (PP) instruction is not executed.
As soon as Chip Select ( S ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed
Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is
protected by the Block Protect (BP1, BP0) bits (see Table 2
and Table 1) is not executed.
Figure 12. Page Program (PP) Instruction Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
Data Byte 1
DIO 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data Byte 2
Data Byte 3
Data Byte 256
DIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
MSB
Note: Address bits A23 to A18 are Don’t Care, for A25L20P.
Address bits A23 to A17 are Don’t Care, for A25L10P.
Address bits A23 to A16 are Don’t Care, for A25L05P
(August, 2007, Version 1.0)
20 AMIC Technology Corp.

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