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PDF MAX9206 Data sheet ( Hoja de datos )
| Número de pieza | MAX9206 | |
| Descripción | (MAX9206 / MAX9208) 10-Bit Bus LVDS Deserializers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2130; Rev 0; 8/01
EVAALVUAAILTAIOBNLEKIT
10-Bit Bus LVDS Deserializers
General Description
The MAX9206/MAX9208 deserializers transform a high-
speed serial bus low-voltage differential signaling
(BLVDS) data stream into 10-bit-wide parallel LVCMOS/
LVTTL data and clock. The deserializers pair with seri-
alizers such as the MAX9205/MAX9207, which gener-
ate a serial BLVDS signal from 10-bit-wide parallel
data. The serializer/deserializer combination reduces
interconnect, simplifies PC board layout, and reduces
board size.
The MAX9206/MAX9208 receive serial data at
400Mbps and 600Mbps, respectively, over board
traces or twisted-pair cables. These devices combine
frequency lock, bit lock, and frame lock to produce a
parallel-rate clock and word-aligned 10-bit data.
Serialization eliminates parallel bus clock-to-data and
data-to-data skew.
A power-down mode reduces typical supply current to
less than 600µA. Upon power-up (applying power or
driving PWRDN high), the MAX9206/MAX9208 estab-
lish lock after receiving synchronization signals or serial
data from the MAX9205/MAX9207. An output enable
allows the outputs to be disabled, putting the parallel
data outputs and recovered output clock into a high-
impedance state without losing lock.
The MAX9206/MAX9208 operate from a single +3.3V
supply and are specified for operation from -40°C to
+85°C. The MAX9206/MAX9208 are available in 28-pin
SSOP packages.
Applications
Cellular Phone Base
Stations
Add/Drop Muxes
DSLAMs
Network Switches and
Routers
Digital Cross-Connects Backplane Interconnect
Features
o Stand-Alone Deserializer (vs. SERDES) Ideal for
Unidirectional Links
o Automatic Clock Recovery
o Allow Hot Insertion and Synchronization Without
System Interruption
o BLVDS Serial Input Rated for Point-to-Point and
Bus Applications
o Fast Pseudorandom Lock
o Wide Reference Clock Input Range
16MHz to 40MHz (MAX9206)
40MHz to 60MHz (MAX9208)
o High 720ps (p-p) Jitter Tolerance (MAX9206)
o Low 30mA Supply Current (MAX9206 at 16MHz)
o 10-Bit Parallel LVCMOS/LVTTL Output
o Up to 600Mbps Throughput (MAX9208)
o Programmable Output Strobe Edge
o Pin Compatible to DS92LV1212A and
DS92LV1224
Ordering Information
PART
TEMP.
RANGE
REF CLOCK PIN-
RANGE (MHz) PACKAGE
MAX9206EAI -40°C to +85°C
MAX9208EAI -40°C to +85°C
16 to 40
40 to 60
28 SSOP
28 SSOP
Pin Configuration appears at end of data sheet.
10
IN_
TCLK_R/F
TCLK
SYNC 1
SYNC 2
Typical Operating Circuit
OUT+
BUS
LVDS
RI+
100Ω
100Ω
10
ROUT_
OUT- RI-
PLL TIMING AND
CONTROL
PC BOARD OR
TWISTED PAIR
EN
PWRDN
PLL
TIMING AND
CONTROL
REFCLK
REN
LOCK
MAX9205
MAX9207
MAX9206
MAX9208
CLOCK
RECOVERY
RCLK
RCLK_R/F
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
10-Bit Bus LVDS Deserializers
PIN
1, 12, 13
2
3
4, 11
5
6
7
8
9
10
14, 20,
22
15–19,
24–28
21, 23
NAME
AGND
RCLK_R/F
REFCLK
AVCC
RI+
RI-
PWRDN
REN
RCLK
LOCK
DGND
ROUT9–
ROUT0
DVCC
Pin Description
FUNCTION
Analog Ground
Strobe Edge Select for Recovered Clock (RCLK). LVTTL/LVCMOS level input. Drive RCLK_ R/F high
to strobe ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling
edge of RCLK.
Reference Clock for PLL. LVTTL/LVCMOS level input.
Analog Power Supply. Bypass AVCC with a 0.1µF and a 0.001µF capacitor to AGND.
Serial Data Input. Noninverting BLVDS differential input.
Serial Data Input. Inverting BLVDS differential input.
Power Down. LVTTL/LVCMOS level input. Drive PWRDN low to stop the PLL and put ROUT_, LOCK,
and RCLK in high impedance.
Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance. LOCK remains active, indicating the status of the serial input.
Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
Lock Indicator. LVTTL/LVCMOS level output. LOCK goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
Digital Ground
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after LOCK goes low.
Digital Power Supply. Bypass DVCC with a 0.1µF and a 0.001µF capacitor to DGND.
Test Circuits/Timing Diagrams
START
START
START
BIT
BIT
END
END BIT
RI
0 1 2 3 4 5 6 7 8 9 BIT
0 1 2 3 4 5 6 7 8 9 BIT
012
RCLK
TDD
ODD
ROUT
RCLK_R/F = HIGH
EVEN
ROUT
Figure 1. Worst-Case ICC Test Pattern
_______________________________________________________________________________________ 5
5 Page 
10-Bit Bus LVDS Deserializers
Table 2. Input/Output Function Table
LOGIC INPUTS
REN
PWRDN
CONDITIONS
X Low Power applied and stable
Low
High
Deserializer initialized
High
X = don’t care
High
Deserializer initialized
OUTPUTS
Power-down mode. PLL is stopped. Current consumption is reduced
to 400µA (typ). ROUT_, RCLK, and LOCK are high impedance.
RCLK and ROUT_ are high impedance. LOCK is active, indicating
the serial input status.
RCLK and ROUT_ are active. LOCK is active, indicating the serial
input status.
Topologies
The MAX9206/MAX9208 deserializers can operate in a
variety of topologies. Examples of double-terminated
point-to-point and point-to-point broadcast are shown
in Figures 10 and 11. Use 1% surface-mount termina-
tion resistors.
A point-to-point interface terminated at each end in the
characteristic impedance of the cable or PC board
traces is shown in Figure 10. The total load seen by the
serializer is 50Ω. The double termination typically
reduces reflections compared to a single 100Ω termi-
nation. A single 100Ω termination at the deserializer
input is feasible and makes the differential signal swing
larger.
A point-to-point version of a multidrop bus is shown in
Figure 11. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to a bus, more interconnect is traded for
robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter is a component of the
total jitter seen at the deserializer input (along with
other sources of jitter), a low-jitter repeater is essential
in most high data-rate applications.
Board Layout
A four-layer PC board providing separate power,
ground, and signal layers is recommended. Keep the
LVTTL/LVCMOS inputs and outputs separated from the
BLVDS inputs to prevent coupling into the BLVDS lines.
Pin Configuration
TOP VIEW
AGND 1
RCLK_R/F 2
REFCLK 3
AVCC 4
RI+ 5
RI- 6
PWRDN 7
REN 8
RCLK 9
LOCK 10
AVCC 11
AGND 12
AGND 13
DGND 14
MAX9206/
MAX9208
SSOP
28 ROUT0
27 ROUT1
26 ROUT2
25 ROUT3
24 ROUT4
23 DVCC
22 DGND
21 DVCC
20 DGND
19 ROUT5
18 ROUT6
17 ROUT7
16 ROUT8
15 ROUT9
Chip Information
TRANSISTOR COUNT: 9602
PROCESS: CMOS
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX9206.PDF ] | |
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