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PDF ALC100 Data sheet ( Hoja de datos )
| Número de pieza | ALC100 | |
| Descripción | Valued AC 97 Audio Codec | |
| Fabricantes | Realtek Semiconductor | |
| Logotipo |  |
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Avance Logic,Inc.
ALC100
ALC100/ALC100P
AC’97 Audio CODEC
Revision 1.1
May 25, 2000
1 page  
www.DataSheet4U.com
Avance Logic,Inc.
ALC100
4. Mixer Register :
All mixer register access with odd-number will return with 0.
Reading unimplemented registers will return 0.
MX00
Reset
Default : 5800h
Bit Type
Function
15 Reserved
14:10
R return 16H
9 R Read as 0 (No support 20-bit ADC)
8 R Read as 0 (No support 18-bit ADC)
7 R Read as 0 (No support 20-bit DAC)
6 R Read as 0 (No support 18-bit DAC)
5 R Read as 0 (No support for Loudness)
4 R Read as 0 (No HeadPhone-Out support)
3 R Read as 0 (No simulated stereo ,for analog 3D block use)
2 R Read as 0 (No Bess & Treble Control)
1 R Reserved,Read as 0
0 R Read as 0 (No Dedicated Mic PCM input)
ΠWrite to this register will reset all mixer registe2r to their default value. The write data is
ignored.
MX02
Master Volume
Default : 8000h
Bit Type
Function
15 R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
14:13
Reserved
12:8 R/W Master Left Volume (MLV[4..0]) in 1.5 dB step
7:5 Reserved
4:0 R/W Master Right Volume (MRV[4..0]) in 1.5 dB step
ΠFor MRV/MLV,
00h 0 dB attenuation
1Fh 46.5 dB attenuation
• MRV/MLV are 5-bit R/W variables. The 6th bit implementation is optional. For this reason,
when 6th bit is written by 1,it is equivalent to writing low 5-bit with 1. For example, writing
MX04
1xxxxx will read back 01111.
Line Level Output Volume
Default : 8000h
Bit Type
Function
15 R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
14:13
Reserved
12:8 R/W Line Level Output Left Volume (LNLV[4..0]) in 1.5 dB step
7:5 Reserved
4:0 R/W Line Level Output Right Volume (LNRV[4..0]) in 1.5 dB step
ΠFor LNRV/LNLV,
00h 0 dB attenuation
1Fh 46.5 dB attenuation
•Implement 5-bit volume control only. Writing 1xxxxx will be interpreted as x11111 and
response when read with x11111 too.
MX06
MONO_OUT Volume
Default : 8000H
Bit Type
Function
15 R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
14:5 Reserved
4:0 R/W Mono Master Volume (MMV[4..0]) in 1.5 dB step
ΠFor MMV,
00h 0 dB attenuation
1Fh 46.5 dB attenuation
•Implement 5-bit volume control only. Writing 1xxxxx will be interpreted as x11111 and
- 5 – Rev 1.1
5 Page 
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Avance Logic,Inc.
ALC100
Fig 5.4-1 Example of differential CD input
5.5 Odd Addressed Register Access :
ALC100 will not response to odd-addressed register access for future compatibility.
5.6 Power-down Mode :
Pay special attention to powerdown control register (index 26h),expecially PR4 (powerdown
AC-link).
5.7 Test Mode :
5.7.1 ATE In Circuit Test Mode :
SDATA_OUT is sampled high at the trailing edge of RESET#. at this mode ALC100 will drive
BIT_CLK
and SDATA_IN to high impedance state.
5.7.2 Vendor Specific Test Mode :
SYNC is sampled high at the trailing edge of RESET#.
6. Electrical Characteristics :
6.1 DC Characteristics :
Dvdd= 5.0V or 3.3V±5%, Tambient=250C, with 50pF external load.
Parameter Symbol Min Typ Max
Input voltage range
Vin -0.30
Low level input voltage
Vil
-
High level input voltage
Vih 0.4DVdd
High level output voltage Voh 0.5DVdd
Low level output voltage
Vol
-
Input leakage current
- -10
- Dvdd+0.30
- 0.35Dvdd
--
--
- 0.2DVdd
- 10
Output leakage current
-
-10
-
10
(Hi-Z)
Output buffer drive current -
-
5
-
6.2 AC Timing Characteristics :
6.2.1 Cold Reset :
Parameter
Symbol Min Typ Max
RESET# active low pulse width Trst_low
RESET# inactive to BIT_CLK Trst2clk
startup delay
1.0
162.8
-
-
-
-
- 11 –
Units
V
V
V
V
V
uA
uA
mA
Units
us
ns
Rev 1.1
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ALC100.PDF ] | |
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