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PDF ATmega328V Data sheet ( Hoja de datos )
| Número de pieza | ATmega328V | |
| Descripción | (ATmegaxxxP/V) 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 4/8/16/32K Bytes of In-System Self-Programmable Flash
(ATmega48P/88P/168P/328P)
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 256/512/512/1K Bytes EEPROM (ATmega48P/88P/168P/328P)
Endurance: 100,000 Write/Erase Cycles
– 512/1K/1K/2K Byte Internal SRAM (ATmega48P/88P/168P/328P)
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
• Operating Voltage:
– 1.8 - 5.5V for ATmega48PV/88PV/168PV/328PV
– 2.7 - 5.5V for ATmega48P/88P/168P/328P
• Temperature Range:
– -40°C to 85°C
• Speed Grade:
– ATmega48PV/88PV/168PV/328PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATmega48P/88P/168P/328P: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Low Power Consumption
– Active Mode:
1 MHz, 1.8V: TBD µA
32 kHz, 1.8V: TBD µA (including Oscillator)
– Power-down Mode:
TBD µA at 1.8V
8-bit
Microcontroller
with 4/8/16/32K
Bytes In-System
Programmable
Flash
ATmega48P/V
ATmega88P/V
ATmega168P/V
ATmega328P/V
Preliminary
Rev. 8025AS–AVR–07/07
1 page  
ATmega48P/88P/168P/328P
2. Overview
The ATmega48P/88P/168P/328P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48P/88P/168P/328P achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
EEPROM
Power
Supervision
POR / BOD &
RESET
Flash
debugWIRE
PROGRAM
LOGIC
SRAM
CPU
8bit T/C 0
8bit T/C 2
16bit T/C 1
Analog
Comp.
A/D Conv.
2
Internal
Bandgap
6
AVCC
AREF
GND
USART 0
SPI
TWI
8025AS–AVR–07/07
PORT D (8)
PORT B (8)
PORT C (7)
PD[0..7]
PB[0..7]
PC[0..6]
ADC[6..7]
RESET
XTAL[1..2]
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
5
5 Page 
ATmega48P/88P/168P/328P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x0 (0x20)
PCIFR
Reserved
Reserved
Reserved
TIFR2
TIFR1
TIFR0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTD
DDRD
PIND
PORTC
DDRC
PINC
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTD7
DDD7
PIND7
–
–
–
PORTB7
DDB7
PINB7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
–
–
–
–
–
–
–
–
ICF1
–
–
–
–
–
–
–
–
–
–
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTD3
DDD3
PIND3
PORTC3
DDC3
PINC3
PORTB3
DDB3
PINB3
–
–
–
PCIF2
–
–
–
OCF2B
OCF1B
OCF0B
–
–
–
–
–
–
–
–
–
PORTD2
DDD2
PIND2
PORTC2
DDC2
PINC2
PORTB2
DDB2
PINB2
–
–
–
PCIF1
–
–
–
OCF2A
OCF1A
OCF0A
–
–
–
–
–
–
–
–
–
PORTD1
DDD1
PIND1
PORTC1
DDC1
PINC1
PORTB1
DDB1
PINB1
–
–
–
PCIF0
–
–
–
TOV2
TOV1
TOV0
–
–
–
–
–
–
–
–
–
PORTD0
DDD0
PIND0
PORTC0
DDC0
PINC0
PORTB0
DDB0
PINB0
–
–
–
164
141
94
94
94
93
93
93
93
93
93
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48P/88P/168P/328P is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for ATmega88P/168P/328P.
8025AS–AVR–07/07
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ATmega328V.PDF ] | |
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