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PDF ePV6200 Data sheet ( Hoja de datos )
| Número de pieza | ePV6200 | |
| Descripción | VFD Controller | |
| Fabricantes | Elan | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ePV6200 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ePV6200
VFD Controller
Version 1.2
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03) 5780617
1 page  
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ePV6200
VFD Controller
Port HV
-
-
-
-
P54 SG1/KS1
P55 SG2/KS2
P56 SG3/KS3
P57 SG4/KS4
Port
P80
P81
P82
P83
P84
P85
P86
P87
HV
GR8
GR7
GR6
GR5
GR4
GR3
GR2
GR1
Port HV
P60 SG5/KS5
P61 SG6/KS6
P62 SG7/KS7
P63 SG8/KS8
P64 SG9/KS9
P65 GR19/SG10/KS10
P66 GR18/SG11/KS11
P67 GR17/SG12/KS12
Port HV
P70 GR16/SG13
P71 GR15 SG14
P72 GR14/SG15
P73 GR13/SG16
P74 GR12/SG17
P75 GR11/SG18
P76 GR10/SG19
P77 GR9/SG20
Port
P90
P91
P92
P93
P94
P95
P96
P97
GPIO
GPIO90/LED0/IR
GPIO91/LED1/INT1
GPIO92/LED2/INT2
GPIO93/LED3/INT3
GPIO94/LED4/INT4
GPIO95/LED5
GPIO96/LED6
GPIO97/LED7
Port
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GPIO
GPIOC0/Key1
GPIOC1/Key2
GPIOC2/Key3
GPIOC3/Key4
GPIOC4/STB
GPIOC5/CLK
GPIOC6/DOUT
GPIOC7/ DIN
Table.2c Ports Mapping for HV and GPIO
This specification is subject to change without further notice.
04/06/2004 (V1.2)
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ePV6200
VFD Controller
CN215 CN214 CN213 CN212 CN211 CN210 CN29 CN28
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 0 ~ Bit 7 (CN28 ~ CN215) : Counter2_HB's buffer that user can read and write.
Counter2 is a 16-bit up-counter with 8-bit prescaler that user can use R9 PAGE2 to preset and read the
counter.(write è preset) After a interruption, it will reload the preset value.
RA (PLL, Main clock selection, Watchdog timer),Counter3 data
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit)
76543 2 10
IDLE PLLEN CLK2 CLK1 CLK0
-
- WDTEN
R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
R/W-0
Bit 0(WDTEN) : Watch dog control bit
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If the
prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the prescaler
assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
0/1 è disable/enable
Bit 1~Bit 2 : Unused
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
PLLEN CLK2 CLK1 CLK0 Sub clock MAIN clock CPU clock
1 0 0 0 32.768kHz 447.829kHz 447.829kHz (Normal mode)
1 0 0 1 32.768kHz 895.658kHz 895.658kHz (Normal mode)
1 0 1 0 32.768kHz 1.791MHz 1.791MHz (Normal mode)
1 0 1 1 32.768kHz 3.582MHz 3.582MHz (Normal mode)
1 1 0 0 32.768kHz 7.165MHz 7.165MHz (Normal mode)
1 1 0 1 32.768kHz 10.747MHz 10.747MHz (Normal mode)
1 1 1 0 32.768kHz 14.331MHz 14.331MHz (Normal mode)
1 1 1 1 32.768kHz 17.91MHz 17.91MHz (Normal mode)
0 Don’t care Don’t care Don’t care 32.768kHz don’t care 32.768kHz (Green mode)
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
0/1 è disable PLL/enable PLL
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode (low
frequency, 32768 Hz).
PLL circuit
Sub-clock
32.768kHz
447.8293kHz ~17.9132MHz
CLK2 ~ CLK0
ENPLL
1
switch
0
System clock
Fig.6 The relation between 32.768kHz and PLL
Bit 7(IDLE) : Sleep mode or IDLE mode control after using "SLEP" instruction.
0/1 è SLEEP mode/IDLE mode.
This bit will decide SLEP instruction which mode to go.
This specification is subject to change without further notice.
04/06/2004 (V1.2)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ePV6200.PDF ] | |
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