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PRELIMINARY
XRT79L71
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
JUNE 2003
GENERAL DESCRIPTION
• JTAG Interface
REV. P1.0.3
The XRT79L71 is a single channel, ATM UNI/PPP
Physical Layer Processor with integrated DS3/E3
framing controller and Line Interface Unit with Jitter
Attenuator that is designed to support ATM direct
mapping and cell delineation as well as PPP mapping
and Frame processing. For ATM UNI applications,
this device provides the ATM Physical Layer (Physical
Medium Dependent and Transmission Convergence
sub-layers) interface for the public and private net-
works at DS3/E3 rates. For Clear-Channel Framer
applications, this device supports the transmission
and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line
Interface Unit with Jitter Attenuator that supports
mapping of ATM or HDLC framed data. A flexible
parallel microprocessor interface is provided for
configuration and control. Industry standard UTOPIA II
and POS-PHY interface are also provided.
GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected
either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single
frequency clock and generates either DS3 or E3
frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/
extraction of either bit or byte mapped
encapsulated packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
and Mips µPs
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 208 STBl PBGA Package
LINE INTERFACE UNIT
• On chip Clock and Data Recovery circuit for high
input jitter tolerance
• Meets E3/DS3 Jitter Tolerance Requirements
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
• Meets ETSI TBR 24 and GR-499 Jitter Transfer
Requirements
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
• On chip advanced crystal-less Jitter Attenuator
• Jitter Attenuator can be selected in Receive or
Transmit paths
• 16 or 32 bits selectable FIFO size
• Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards
• Jitter Attenuator can be disabled
• Typical power consumption 1.3W
DS3/E3 FRAMER
• DS3 framer supports both M13 and C-bit parity.
• DS3 framer meets ANSI T1.107 and T1.404
standards.
• Detects OOF,LOF,AIS,RDI/FERF alarms.
• Generation and Insertion of FEBE on received
parity errors supported.
• Automatic insertion of RDI/FERF on alarm status.
• E3 framer meets G.832,G.751 standards.
• Framers can be bypassed.
ATM/PPP PROTOCOL PROCESSOR
TRANSMIT CELL PROCESSING
• Extracts ATM cells
• Supports ATM cell payload scrambling
• Maps ATM cells into E3 or DS3 frame
• PLCP frame and mapping of ATM cell streams
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
E3 LINE SIDE PARAMETERS ......................................................................................................................... 46
FIGURE 10. PULSE MASK FOR E3 (34.368MBPS) INTERFACE AS PER ITU-T G.703 ......................................................................... 46
TABLE 7: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ....................................................... 46
DS3 LINE SIDE PARAMETERS ...................................................................................................................... 47
FIGURE 11. BELLCORE GR-499-CORE PULSE TEMPLATE REQUIREMENTS FOR DS3 APPLICATIONS................................................ 47
TABLE 8: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 48
TABLE 9: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 48
TRANSMIT UTOPIA INTERFACE ................................................................................... 49
FIGURE 12. TIMING DIAGRAM FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ................................................................................ 49
TABLE 10: TIMING INFORMATION FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ........................................................................... 49
TRANSMIT PAYLOAD DATA INPUT INTERFACE ........................................................ 50
TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS..................................... 50
TABLE 11: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................ 50
FIGURE 13. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3
AND LOOP-TIMING MODES .............................................................................................................................................. 51
FIGURE 14. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3
AND LOCAL-TIMING MODES............................................................................................................................................. 52
FIGURE 15. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOOP-TIMING MODES .................................................................................................................. 52
FIGURE 16. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOCAL-TIMING MODES................................................................................................................. 53
TRANSMIT OVERHEAD DATA INPUT INTERFACE...................................................... 54
TRANSMIT OVERHEAD DATA INPUT INTERFACE - TIMING REQUIREMENTS.................................. 54
TABLE 12: TIMING INFORMATION FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ..................................................... 54
FIGURE 17. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 1 ACCESS) .................................... 56
FIGURE 18. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 2 ACCESS) .................................... 56
RECEIVE PAYLOAD DATA OUTPUT INTERFACE ....................................................... 57
RECEIVE PAYLOAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................... 57
TABLE 13: TIMING INFORMATION FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ...................................................... 57
FIGURE 19. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (SERIAL MODE).............................................. 57
FIGURE 20. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (NIBBLE-PARALLEL MODE) ............................. 58
RECEIVE OVERHEAD DATA OUTPUT INTERFACE .................................................... 59
RECEIVE OVERHEAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................ 59
AC ELECTRICAL CHARACTERISTICS (CONT.)................................................................................................. 59
FIGURE 21. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 1 - USING RXOHCLK) .................. 60
FIGURE 22. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 2 - USING RXOHENABLE) ............ 60
RECEIVE UTOPIA INTERFACE ...................................................................................... 61
RECEIVE UTOPIA INTERFACE ............................................................................................................... 61
FIGURE 23. TIMING DIAGRAM FOR THE RECEIVE UTOPIA INTERFACE BLOCK .................................................................................. 61
TABLE 14: TIMING INFORMATION FOR THE RECEIVE UTOPIA INTERFACE BLOCK ............................................................................. 61
REGISTER MAP OF THE XRT79L71 ............................................................................. 63
COMMONCONTROL REGISTERS OF THE XRT79L71 ...................................................................................... 63
CLEAR-CHANNEL FRAMER BLOCK REGISTERS ................................................................................. 64
LIU/JITTER ATTENUATOR CONTROL REGISTERS .............................................................................. 68
RECEIVE ATM CELL PROCESSOR/PPP PROCESSOR BLOCK CONTROL REGISTERS................... 69
OPERATION BLOCK INTERRUPT REGISTER BIT FORMATS .................................... 77
OPERATION CONTROL REGISTER - BYTE 3 (ADDRESS = 0X0100) ................................................................. 77
OPERATION CONTROL REGISTER - BYTE 2 (ADDRESS = 0X0101) ................................................................. 77
OPERATION CONTROL - LOOP-BACK CONTROL REGISTER (ADDRESS = 0X0102) ........................................... 78
OPERATION CONTROL REGISTER - BYTE 0 (ADDRESS = 0X0103) ................................................................. 79
DEVICE ID REGISTER (ADDRESS = 0X0104) ................................................................................................. 79
REVISION ID REGISTER (ADDRESS = 0X0105).............................................................................................. 80
OPERATION INTERRUPT STATUS REGISTER - BYTE 1 (ADDRESS = 0X0112) .................................................. 80
OPERATION INTERRUPT STATUS REGISTER - BYTE 0 (ADDRESS = 0X0113) .................................................. 81
OPERATION INTERRUPT ENABLE REGISTER - BYTE 1 (ADDRESS = 0X0116) .................................................. 82
OPERATION INTERRUPT ENABLE REGISTER - BYTE 0 (ADDRESS = 0X0117) .................................................. 83
CHANNEL INTERRUPT INDICATION REGISTERS ....................................................... 84
CHANNEL INTERRUPT INDICATOR - RECEIVE CELL PROCESSOR/PPP PROCESSOR BLOCK (ADDRESS = 0X0119)84
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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
4 (ADDRESS = 0X1757) ............................................................................................................................. 302
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - CHECK REGISTER - BYTE 1 (ADDRESS
= 0X1758) ................................................................................................................................................ 303
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - CHECK REGISTER - BYTE 2 (ADDRESS
= 0X1759) ................................................................................................................................................ 304
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - CHECK REGISTER - BYTE 3 (ADDRESS
= 0X175A) ................................................................................................................................................ 305
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - CHECK REGISTER - BYTE 4 (ADDRESS
= 0X175B) ................................................................................................................................................ 306
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - FILTERED CELL COUNT - BYTE 3 (AD-
DRESS = 0X175C) ..................................................................................................................................... 307
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - FILTERED CELL COUNT - BYTE 2 (AD-
DRESS = 0X175D) ..................................................................................................................................... 308
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - FILTERED CELL COUNT - BYTE 1 (AD-
DRESS = 0X175E) ..................................................................................................................................... 309
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 1 - FILTERED CELL COUNT - BYTE 0 (AD-
DRESS = 0X175F) ..................................................................................................................................... 310
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER CONTROL - FILTER 2 (ADDRESS = 0X1763)
311
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - PATTERN REGISTER - HEADER BYTE
1 (ADDRESS = 0X1764) ............................................................................................................................. 313
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - PATTERN REGISTER - HEADER BYTE
2 (ADDRESS = 0X1765) ............................................................................................................................. 314
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - PATTERN REGISTER - HEADER BYTE
3 (ADDRESS = 0X1766) ............................................................................................................................. 315
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - PATTERN REGISTER - HEADER BYTE
4 (ADDRESS = 0X1767) ............................................................................................................................. 316
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - CHECK REGISTER - BYTE 1 (ADDRESS
= 0X1768) ................................................................................................................................................ 317
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - CHECK REGISTER - BYTE 2 (ADDRESS
= 0X1769) ................................................................................................................................................ 318
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - CHECK REGISTER - BYTE 3 (ADDRESS
= 0X176A) ................................................................................................................................................ 319
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - CHECK REGISTER - BYTE 4 (ADDRESS
= 0X176B) ................................................................................................................................................ 320
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - FILTERED CELL COUNT - BYTE 3 (AD-
DRESS = 0X176C) ..................................................................................................................................... 321
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - FILTERED CELL COUNT - BYTE 2 (AD-
DRESS = 0X176D) ..................................................................................................................................... 322
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - FILTERED CELL COUNT - BYTE 1 (AD-
DRESS = 0X176E) ..................................................................................................................................... 323
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 2 - FILTERED CELL COUNT - BYTE 0 (AD-
DRESS = 0X176F) ..................................................................................................................................... 324
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER CONTROL - FILTER 3 (ADDRESS = 0X1773)
325
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 3 - PATTERN REGISTER - HEADER BYTE
1 (ADDRESS = 0X1774) ............................................................................................................................. 326
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 3 - PATTERN REGISTER - HEADER BYTE
1 (ADDRESS = 0X1774) ............................................................................................................................. 328
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 3 - PATTERN REGISTER - HEADER BYTE
2 (ADDRESS = 0X1775) ............................................................................................................................. 329
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 3 - PATTERN REGISTER - HEADER BYTE
3 (ADDRESS = 0X1776) ............................................................................................................................. 330
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE USER CELL FILTER # 3 - PATTERN REGISTER - HEADER BYTE
4 (ADDRESS = 0X1777) ............................................................................................................................. 331
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