PDF CY28435 Data sheet ( Hoja de datos )

Número de pieza	CY28435
Descripción	Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com PRELIMINARY CY28435 Clock Generator for Intel Grantsdale Chipset Features • Compliant to Intel CK410 • Supports Intel Prescott and Tejas CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96-MHz differential dot clock • 48-MHz USB clocks • 33-MHz PCI clock • Dynamic Frequency Control Block Diagram • Dial-A-Frequency • Watchdog • Two Independent Overclocking PLLs • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages CPU SRC PCI REF DOT96 USB x2 x7 x9 x2 x1 x2 Pin Configuration Xin 14.318MHz Xout Crystal PLL Reference FS_[E:A] CPU PLL Divider SRC PLL Divider SDATA PLL Divider VTTPWR_GD#/PD DF_EN DF[2:0] SDATA SCLK FIX PLL Divider Dynamic Frequency I2C Logic Watchdog Timer VDD_RE F RE F IREF VDD_CPU CPUT CPUC VDD_CPU ITP_EN VDD_SRC SRCT SRCC VDD_SRC VDD_SRC SRCT4_SATA SRCC4_SATA VDD_48Mhz DOT96T DOT96C VDD_48 USB VDD_PCI PCI VDD_PCI PCIF SRESET# VDD_PCI VSS_PCI DF2/PCI3 FS_E/PCI4 PCI5 VSS_PCI VDD_PCI DF_EN/PCIF0 SRESET_EN/PCIF1 PCIF2 VDD_48 USB48_0 VSS_48 DOT96T DOT96C FS_B/USB48_1 VTTPWRGD#/PD FS_A SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRCT4_SATA SRCC4_SATA VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 PCI2/DF1 55 PCI1/DF0 54 PCI0/SRESET# 53 REF1/FS_C 52 REF0/FS_D 51 VSS_REF 50 XIN 49 XOUT 48 VDD_REF 47 SDATA 46 SCLK 45 VSS_CPU 44 CPUT0 43 CPUC0 42 VDD_CPU 41 CPUT1 40 CPUC1 39 IREF 38 VSSA 37 VDDA 36 SRCT7 35 SRCC7 34 VDD_SRC 33 SRCT6 32 SRCC6 31 SRCT5 30 SRCC5 29 VSS_SRC * indicates internal pull-up ** indicates internal pull-down Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07664 Rev. B Revised December 21, 2004 1 page PRELIMINARY CY28435 Table 3. Byte Read and Byte Write Protocol (continued) Bit 18:11 19 27:20 28 29 Byte Write Protocol Description Command Code – 8 bits Acknowledge from slave Data byte – 8 bits Acknowledge from slave Stop Bit 18:11 19 20 27:21 28 29 37:30 38 39 Byte Read Protocol Description Command Code – 8 bits Acknowledge from slave Repeated start Slave address – 7 bits Read Acknowledge from slave Data from slave – 8 bits NOT Acknowledge Stop Control Registers Byte 0: Control Register 0 Bit @Pup 71 Name SRC[T/C]7 61 SRC[T/C]6 51 SRC[T/C]5 4 1 SRC[T/C]4_SATA 31 SRC[T/C]3 21 SRC[T/C]2 11 SRC[T/C]1 01 RESERVED Description SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4_SATA Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable RESERVED, Set = 1 Byte 1: Control Register 1 Bit @Pup 71 61 51 41 30 21 11 00 Name PCIF0 DOT_96T/C USB48_0 REF0 RESERVED CPU[T/C]1 CPU[T/C]0 CPU Description PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB48_0 MHz Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled RESERVED, Set = 0 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Document #: 38-07664 Rev. B Page 5 of 23 5 Page PRELIMINARY CY28435 Table 4. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut Loading Load Cap AT Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap Motional (max.) (max.) 5 pF 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm Figure 2. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci1 Ci2 Pin 3 to 6p X1 Cs1 X2 Cs2 XTAL Trace 2.8pF As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capac- itance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 ( Ce1 + 1 Cs1 + Ci1 + Ce2 + 1 Cs2 + Ci2 ) CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) Ce1 Ce2 Trim 33pF Figure 3. Crystal Loading Example Document #: 38-07664 Rev. *B Page 11 of 23 11 Page

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