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PDF 3D3622 Data sheet ( Hoja de datos )
| Número de pieza | 3D3622 | |
| Descripción | 22-BIT PROGRAMMABLE PULSE GENERATOR | |
| Fabricantes | Data Delay Devices | |
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22-BIT PROGRAMMABLE PULSE
GENERATOR
(SERIES 3D3622 – SERIAL INTERFACE)
3D3622
ddaeltaay 3
devices, inc.
FEATURES
PACKAGE / PINOUT
• All-silicon, low-power CMOS technology
• 3.3V operation
• Vapor phase, IR and wave solderable
• Programmable via serial interface
• Increment range: 0.25ns through 50.0ns
• Pulse width tolerance: 1% (See Table 1)
• Supply current: 8mA typical
• Temperature stability: ±1.5% max (-40C to 85C)
• Vdd stability: ±1.0% max (3.0V to 3.6V)
TRIG 1 14 VDD
RES 2 13 OUT
GND 3 12 OUTB
NC 4 11 SI
NC 5 10 SC
SO 6
9 NC
GND 7
8 AE
3D3622D-xx SOIC
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3622 device is a versatile 22-bit programmable monolithic
pulse generator. A rising-edge on the trigger input (TRIG) initiates
the pulse, which is presented on the output pins (OUT,OUTB). The
pulse width, programmed via the serial interface, can be varied
over 4,194,303 equal steps according to the formula:
tPW = tinh + addr * tinc
where addr is the programmed address, tinc is the pulse width
increment (equal to the device dash number), and tinh is the
inherent (address zero) pulse width. The device also offers a reset
input (RES), which can be used to terminate the pulse before the
programmed time has expired.
The all-CMOS 3D3622 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL pulse generators. It is
offered in a standard 14-pin SOIC.
TRIG Trigger Input
RES Reset Input
OUT Pulse Output
OUTB Complementary
Pulse Output
AE Address Enable Input
SC Serial Clock Input
SI Serial Data Input
SO Serial Data Output
VDD +3.3 Volts
GND Ground
NC No Internal Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D3622D-0.25
3D3622D-0.4
3D3622D-0.5
3D3622D-1
3D3622D-2
3D7622D-2.5
3D3622D-4
3D3622D-5
3D3622D-10
3D3622D-20 *
3D7622D-25 *
3D3622D-40 *
3D3622D-50 *
Pulse Width
Step (ns)
0.25 ± 0.12
0.40 ± 0.20
0.50 ± 0.25
1.00 ± 0.50
2.00 ± 1.00
2.50 ± 1.25
4.00 ± 2.00
5.00 ± 2.50
10.0 ± 5.00
20.0 ± 10.0
20.0 ± 10.0
40.0 ± 20.0
50.0 ± 25.0
Minimum
P.W. (ns)
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
15.0 ± 5.0
24.0 ± 6.0
42.0 ± 8.0
15.0 ± 5.0
15.0 ± 5.0
15.0 ± 5.0
Maximum
Pulse Width
1.05 ms ± 10 us
1.68 ms ± 17 us
2.10 ms ± 21 us
4.19 ms ± 42 us
8.39 ms ± 84 us
10.5 ms ± 105 us
16.8 ms ± 170 us
21.0 ms ± 210 us
41.9 ms ± 420 us
83.9 ms ± 840 us
105 ms ± 1.0 ms
168 ms ± 1.7 ms
210 ms ± 2.1 ms
NOTES: Any increment between 0.25 and 50 ns not shown is also available as a standard device.
* Some restrictions apply to dash numbers greater than 15. See application notes for more details.
2006 Data Delay Devices
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page  
DEVICE SPECIFICATIONS
3D3622
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
IIN
TSTRG
TLEAD
MIN MAX UNITS NOTES
-0.3 7.0 V
-0.3 VDD+0.3 V
-10 10 mA
25C
-55 150 C
300 C 10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output
Current
Low Level Output Current
SYMBOL
IDD
VIH
VIL
IIH
IIL
IOH
IOL
MIN
2.0
4.0
Output Rise & Fall Time
TR & TF
*IDD(Dynamic) = 2 * CLD * VDD * F
where: CLD = Average capacitance load/output (pf)
F = Trigger frequency (GHz)
TYP
8.0
-35.0
15.0
2.0
MAX
12.0
0.8
1.0
1.0
-4.0
UNITS
mA
V
V
µA
µA
mA
mA
2.5 ns
NOTES
VIH = VDD
VIL = 0V
VDD = 3.0V
VOH = 2.4V
VDD = 3.0V
VOL = 0.4V
CLD = 5 pf
Input Capacitance = 5 pf typical
Output Load Capacitance (CLD) = 25 pf max
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
Trigger Width
Trigger Inherent Delay
Output Pulse Width
Re-trigger Time
Reset Width
Reset to Output Low
End of Reset to Next Trigger
AE High to First Clock Edge
AE High to Serial Output Valid
Serial Clock Width
Data Setup to Clock
Data Hold from Clock
Clock to Serial Output
Last Clock Edge to AE Low
Output Low to AE Low
AE Low to Serial Output High-Z
AE Low to Trigger
SYMBOL
tTW
tID
tPW
tRTO
tRW
tRD
tRTR
tES
tEV
tCW
tDS
tDH
tCQ
tEH
tOA
tEX
tAT
MIN
5
3
TBD
3
10
8
10
3
8
TBD
10
TYP
MAX
5
5
20
8
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REFER TO
Figure 2 & 3
Figure 2 & 3
Figure 2
Figure 2
Figure 3
Figure 3
Figure 3
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 3D3622.PDF ] | |
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