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PDF LTC2621 Data sheet ( Hoja de datos )
| Número de pieza | LTC2621 | |
| Descripción | (LTC2601 - LTC2621) 12-Bit Rail-to-rail DACs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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1. LTC2621 datasheet  Hay una vista previa y un enlace de descarga de LTC2621 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
s Smallest Pin-Compatible Single DACs:
LTC2601: 16 Bits
LTC2611: 14 Bits
LTC2621: 12 Bits
s Guaranteed Monotonic Over Temperature
s Wide 2.5V to 5.5V Supply Range
s Low Power Operation: 300µA at 3V
s Power Down to 1µA, Max
s High Rail-to-Rail Output Drive (±15mA, Min)
s Double-Buffered Data Latches
s Asynchronous DAC Update Pin
s Tiny (3mm × 3mm) 10-Lead DFN Package
U
APPLICATIO S
s Mobile Communications
s
www.DataSheet4U.com
Process
Control
and
Industrial
Automation
s Instrumentation
s Automatic Test Equipment
LTC2601/LTC2611/LTC2621
16-/14-/12-Bit Rail-to-Rail
DACs in 10-Lead DFN
DESCRIPTIO
The LTC®2601/LTC2611/LTC2621 are single 16-, 14-
and 12-bit, 2.5V-to-5.5V rail-to-rail voltage output DACs
in a 10-lead DFN package. They have built-in high perfor-
mance output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive, and load regulation in single-supply,
voltage-output multiples.
The parts use a simple SPI/MICROWIRETM compatible
3-wire serial interface which can be operated at clock rates
up to 50MHz. Daisy-chain capability, hardware CLR and
asynchronous DAC update (LDAC) pins are included.
The LTC2601/LTC2611/LTC2621 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; and after power-up, they
stay at zero scale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
U.S. patent number 5396245.
BLOCK DIAGRA
SDI
2
SCK
3
CS/LD
5
SDO
1
6
REF
32-BIT
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
CONTROL
DECODE
LOGIC
LDAC
10
CLR
4
9
VCC
12-/14-/16-BIT DAC
VOUT
7
GND
8
2601 BD
Differential Nonlinearity (LTC2601)
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152 65535
2600 G02
2601f
1
1 page  
LTC2601/LTC2611/LTC2621
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2601
Integral Nonlinearity (INL)
32
VCC = 5V
24 VREF = 4.096V
16
8
0
–8
–16
–24
–32
0
16384
32768
CODE
49152 65535
2601 G01
Differential Nonlinearity (DNL)
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2600 G02
INL vs Temperature
32
VCC = 5V
24 VREF = 4.096V
16
8 INL (POS)
0
–8
INL (NEG)
–16
–24
–32
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
2601 G03
DNL vs Temperature
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
www.DataSheet4U.com 0.2
DNL (POS)
0
–0.2
DNL (NEG)
–0.4
–0.6
–0.8
–1.0
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
2601 G04
INL vs VREF
32
VCC = 5.5V
24
16
8 INL (POS)
0
–8 INL (NEG)
–16
–24
–32
0123
VREF (V)
45
2601 G05
DNL vs VREF
1.5
VCC = 5.5V
1.0
0.5
DNL (POS)
0
DNL (NEG)
–0.5
–1.0
–1.5
012345
VREF (V)
2601 G06
Settling to ±1LSB
Settling of Full-Scale Step
VOUT
100µV/DIV
CS/LD
2V/DIV
9.7µs
2µs/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2601 G07
VOUT
100µV/DIV
CS/LD
2V/DIV
12.3µs
5µs/DIV
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
2601 G08
2601f
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5 Page 
U
OPERATIO
Power-On Reset
The LTC2601/LTC2611/LTC2621 clear the outputs to zero
scale when power is first applied, making system initializa-
tion consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2601/
LTC2611/LTC2621 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limitswww.DataSheet4U.com during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is:
VOUT(IDEAL)
=
k
2N
VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 6).
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then 4 don’t
care bits; and finally the 16-bit data word. The data word
comprises the 16-, 14- or 12-bit input code, ordered MSB-
to-LSB, followed by 0, 2 or 4 don’t care bits (LTC2601,
LTC2611 and LTC2621 respectively). Data can only be
transferred to the device when the CS/LD signal is low.The
rising edge of CS/LD ends the data transfer and causes the
LTC2601/LTC2611/LTC2621
device to execute the command specified in the 24-bit
input word. The complete sequence is shown in Figure 2a.
The command (C3-C0) assignments are shown in Table 1.
The first four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register
of the DAC. In an update operation, the data word is copied
from the input register to the DAC register and converted
to an analog voltage at the DAC output. The update
operation also powers up the DAC if it had been in power-
down mode. The data path and registers are shown in the
Block Diagram.
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits are transferred to the device first, fol-
lowed by the 24-bit word as just described. Figure 2b
shows the 32-bit sequence. The 32-bit word is required for
daisy-chain operation, and is also available to accommo-
date microprocessors which have a minimum word width
of 16 bits (2 bytes).
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy chain” series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire chain.
Table 1.
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power Up) DAC Register
0 0 1 1 Write to and Update (Power Up)
0 1 0 0 Power Down
1 1 1 1 No Operation
*Command codes not shown are reserved and should not be used.
2601f
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC2621.PDF ] | |
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