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PDF IP1201PBF Data sheet ( Hoja de datos )
| Número de pieza | IP1201PBF | |
| Descripción | Dual Output Full Function 2 Phase Synchronous Buck Power Block Integrated Power Semiconductors | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IP1201PBF (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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PD-97109
Features
• 3.14V to 5.5V input voltage
• 0.8V to 3.3V output voltage
• 2 Phase Synchronous Buck Power Block
• 180° out of phase operation
• Single or Dual output capability
• Dual 15A maximum load capability
• Single 2 phase 30A maximum load capability
• 200-400kHz per channel nominal switching frequency
• Over Current Hiccup or Over Current Latch
• External Synchronization capability
• Overvoltage protection
• Independent soft start per output
• Over Temperature protection
• Internal features minimize layout sensitivity *
• Very small outline 15.5mm x 9.25mm x 2.6mm
iP1201PbF
Dual Output Full Function 2 Phase
Synchronous Buck Power Block
Integrated Power Semiconductors,
PWM Control & Passives
iP1201PbF Power Block
Description
The iP1201PbF is a fully optimized solution for medium current synchronous buck applications requiring up to 15A
orwww.DataSheet4U.com 30A. The iP1201PbF is optimized for 2 phase single output applications up to 30A or dual output, each up to
15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chip-sets and
associated passives, achieving high power density. Very few external components are required to create a complete
synchronous buck power supply.
iPOWIR technology offers designers an innovative space-saving solution for applications requiring high power
densities. iPOWIR technology eases design for applications where component integration offers benefits in
performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1201PbF Configurations
Channel 1
V IN
V OUT
V IN
V OUT
Channel 2
V OUT
Single Output
Dual Output
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be applied
for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The iPOWIR block
will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long
term operation. See layout guidelines in datasheet for more detailed information.
www.irf.com
8/11/06
1
1 page  
iP1201PbF
12
11
10
9
8
7
6
5
4
3
2
1
0
0
16 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
www.irf.com
VIN = 5V
VOUT1 = VOUT2 = 1.5V
fSW = 300kHz
L = 1.8µH
TBLK = 125°C
M aximum
T ypical
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Output Current Per Channel (A)
Fig. 2: Power Loss vs. Current
Case Tem perature (&
10 20 30 40 50 60 70 80 90 100 110 120
Safe
Operating
Area
VIN = 5V
V OUT 1 = V OUT 2 = 1.5V
IOUT = 15A
f SW = 300kHz
L = 1.8uH
TX
10 20 30 40 50 60 70 80 90 100 110 120
PCB Te m pe rature (ºC)
Fig. 3: Safe Operating Area (SOA) vs. TPCB & TCASE
5
5 Page 
iP1201PbF
400
380
360
340
320
300
280
260
240
220
200
20 25 30 35 40 45 50
RT in kOhms
VSW1
FB1
iP1iP210210P1bF
FB2
VSW2
Fig. 11: Per Channel Switching Frequency vs RT
Iin Average
V Vin Average Cin
A
Vin DC
PPP+IOLNOUSTS+===((VPVVIIONNOUUA-TT2v1PAeAOvrUvaeTegrraeagxgeeIIxNxAIOIvUOeTU2rTAa1 gvAeevreargaeg)e)
Iout1 Average
Lo1 A Vout1
Co1
Iout1
Averaging
Circuit 1
V Vout1 Average
Iout2 Average
Lo2 Vout2
A
Co2
Iout2
Averaging
Circuit 2
V Vout2 Average
www.irf.com
Fig. 12: Power Loss Test Circuit
11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet IP1201PBF.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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