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PDF ISL6208A Data sheet ( Hoja de datos )

Número de pieza ISL6208A
Descripción High Voltage Synchronous Rectified Buck MOSFET Driver
Fabricantes Intersil Corporation 
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®
Data Sheet
February 15, 2006
ISL6208A
FN9272.0
High Voltage Synchronous Rectified Buck
MOSFET Driver
The ISL6208A is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology. It is
especially suited for mobile computing applications that
require high efficiency and excellent thermal performance.
This driver, combined with an Intersil multiphase Buck PWM
controller, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
The ISL6208A features 4A typical sinking current for the
lower gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the Phase node.
This prevents shoot-through power loss caused by the high
dv/dt of phase voltages. The operating voltage matches the
30V breakdown voltage of the MOSFETs commonly used in
mobile computer power supplies.
The ISL6208A also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown.
This feature eliminates a protective Schottky diode usually
seen in a microprocessor power systems.
MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208A. Each driver is capable of driving a 3000pF
load with propagation delays of 15ns and transition times
under 10ns. Bootstrapping is implemented with an internal
Schottky diode. This reduces system cost and complexity,
while allowing the use of higher performance MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.
A diode emulation feature is integrated in the ISL6208A to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into pre-biased
outputs. When diode emulation is enabled, the driver will
allow discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off
the low side MOSFET gate. Programmable dead-time
control with gate threshold monitoring is also integrated to
prevent both MOSFETs from conducting simultaneously.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”
• Technical Brief TB447 “Guidelines for Preventing Boot-to-
Phase Stress on Half-Bridge MOSFET Driver ICs”
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adaptive Shoot-Through Protection
- Active Gate Threshold Monitoring
- Programmable Dead-Time
• 0.5On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency up to 2MHz
- Fast Output Rise and Fall Time
- Low Propagation Delay
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
• Low Bias Supply Current (5V, 100µA)
• Diode Emulation for Efficiency and Pre-Biased Startup
• VCC POR (Power-On-Reset) Feature Integrated
• Pin-to-pin Compatible with ISL6207, ISL6208, ISL6209
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Supplies for Intel® and AMD® Mobile Microprocessors
• High Frequency, Low Profile DC/DC Converters
• High Current Low Output Voltage DC/DC Converters
• High Input Voltage DC/DC Converters
Ordering Information
PART
PART NUMBER MARKING
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG.
#
ISL6208ACBZ ISL6208ACBZ -10 to 100 8 Ld SOIC
(Note)
(Pb-Free)
M8.15
ISL6208ACBZ-T ISL6208ACBZ 8 Ld SOIC Tape and Reel
(Note)
(Pb-Free)
ISL6208ACRZ 08AZ
(Note)
-10 to 100 8 Ld 3x3 QFN L8.3x3
(Pb-Free)
ISL6208ACRZ-T 08AZ
(Note)
8 Ld 3x3 QFN Tape and Reel
(Pb-Free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6208A pdf
ISL6208A
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see
the three-state PWM Input section under DESCRIPTION for
further details). Connect this pin to the PWM output of the
controller.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin for the IC.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
FCCM (Pin 7 for SOIC-8, Pin 6 for QFN)
The FCCM pin enables or disables Diode Emulation. When
FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced. See the Diode
Emulation section under DESCRIPTION for more detail.
This pin can also be used to program additional switching
dead-time by placing a resistor in series with the input. See
the Programmable Dead-Time section for more detail.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Description
Theory of Operation
Designed for speed, the ISL6208A dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [tPDLL], the lower gate begins to fall. Typical fall times
[tFL] are provided in the Electrical Specifications section.
Adaptive shoot-through circuitry monitors the LGATE
voltage. When LGATE has fallen below 1V, UGATE is
allowed to turn ON. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shoot-
through.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLU] is encountered before the upper
gate begins to fall [tFU]. The upper MOSFET gate-to-source
voltage is monitored, and the lower gate is allowed to rise
after the upper MOSFET gate-to-source voltage drops below
1V. The lower gate then rises [tRL], turning on the lower
MOSFET.
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement.
The 0.5on-resistance and 4A sink current capability
enable the lower gate driver to absorb the current injected to
the lower gate through the drain-to-gate capacitor of the
lower MOSFET and prevent a shoot through caused by the
high dv/dt of the phase node.
5 FN9272.0
February 15, 2006

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