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PDF HI1179 Data sheet ( Hoja de datos )
| Número de pieza | HI1179 | |
| Descripción | Video A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HI1179 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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HI1179
August 1997
8-Bit, 35 MSPS, Video A/D Converter
Features
Description
• Resolution 8-Bit . . . . . . . . . . . . . . . . . . ±0.5 LSB (DNL)
• ENOB at fIN = 1MHz . . . . . . . . . . . . . . . . . . . . . . 7.6 Bits
• Maximum Sampling Frequency . . . . . . . . . . . 35 MSPS
• Low Power Consumption 80mW (at 35 MSPS Typ)
(Reference Current Excluded)
• Built-In Input Clamp Function (DC Restore)
• No Sample/Hold Required
• Internal Voltage Reference
• Input CMOS Compatible
• Three-State TTL Compatible Output
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 8pF
• Reference Impedance (Typ) . . . . . . . . . . . . . . . . . 330Ω
• Direct Replacement for Sony CXD1179
Applications
The HI1179 is an 8-bit CMOS analog-to-digital converter for
video use that features a sync clamp function. The adoption
of a 2-step parallel method realizes low power consumption
and a maximum conversion speed of 35 MSPS, allowing up
to 8x over sampling of NTSC and PAL signals.
The HI1179 is available in the Industrial temperature range
and is supplied in 32 lead Plastic Metric Quad Flatpack
(MQFP) package. For lower sampling rates, refer to the
HI1176 data sheet.
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PACKAGE PKG. NO.
HI1179JCQ
-40 to 85
32 Ld MQFP Q32.7x7-S
HI1179-EV
25 Evaluation Board
• Desktop Video
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Pinout
HI1179 (MQFP)
TOP VIEW
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
VRB
AVSS
AVSS
VIN
AVDD
AVDD
VRT
VRTS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-1110
File Number 3666.3
1 page  
Timing Diagrams
CLOCK
ANALOG INPUT
DATA OUTPUT
tPW1
tPW0
N
N-3
HI1179
N+1
N-2
: POINT FOR ANALOG SIGNAL SAMPLING
tD = 13ns
FIGURE 12.
N-2
N-1
N+3
N
N+4
N+1
ANALOG INPUT
VI (1)
VI (2)
VI (3)
VI (4)
EXTERNAL CLOCK
UPPER COMPARATOR BLOCK
UPPER DATA
S (1)
C (1) S (2) C (2)
S (3) C (3)
S (4) C (4)
MD (0)
MD (1)
MD (2)
MD (3)
LOWER REFERENCE VOLTAGE
RV (0)
RV (1)
RV (2)
RV (3)
LOWER COMPARATOR BLOCK A
LOWER DATA A
S (1)
H (1)
LD (-1)
C (1)
S (3)
H (3)
LD (1)
C (3)
LOWER COMPARATOR BLOCK B
LOWER DATA B
H (0)
C (0) S (2)
LD (-2)
H (2)
LD (0)
C (2)
S (4)
H (4)
LD (2)
DIGITAL OUTPUT
OUT (-2)
OUT (-1)
FIGURE 13.
OUT (0)
OUT (1)
4-1114
5 Page 
HI1179
function is enabled by tying CLE low. In this case a negative
going pulse is sent to the CLP pin. VIN will now be clamped
during the low period of the clamp pulse to the voltage on
the VREF pin. Figure 15 shows the HI1179 configured for
this mode of operation.The clamp pulse is latched by the
ADC sampling clock through an external latch. This is not
necessary to the operation of the clamp function but in video
applications, if this is not done, then a slight beat might be
generated as vertical sag according to the relation between
the sampling frequency and the clamp frequency. The pulse
width of the input clamp pulse will depend on the input
signal. For example, a 1µs pulse width will allow the user to
clamp the back porch of an NTSC input signal to the
reference voltage, VREF.
The clamp can be disabled by tying CLE high and then the
HI1179 acts like a normal A/D converter, accepting a DC
coupled input. The Typical Application Schematic illustrates
the operation of HI1179 when the clamp function is not used.
Additional information on the HI1179 is available in
Application Note 9407, “Using the HI1176/HI1179 Evaluation
Board”.
Test Circuits
+V
S2
- S1: ON IF A < B
+ S1 S2: ON IF A > B
-V
VIN DUT
HI1179
A<B A>B
COMPARATOR
8
A8 B8
8
DVM
A1
A0
“0”
CLK (35MHz)
B1
B0
“1”
CONTROLLER
BUFFER
000 • • • 00
8 TO
111 • • • 10
FIGURE 23. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT
2.6V
fC -1kHz
SG
0.6V
1
AMP
2
VIN DUT
HI1179
NTSC
SIGNAL
40 IRE
SOURCE 100 MODULATION
2.6V
IRE
0
- 40
BURST
SYNC
0.6V
SG
(CW)
fC
8 TTL
ECL
TTL
ECL
HI20201
1
8 10-BIT
D/A 2
CLK
620
-5.2V
620
-5.2V
ERROR RATE
HPF
COUNTER
VECTOR
SCOPE
DG
DP
FIGURE 24. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT
4-1120
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HI1179.PDF ] | |
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