PDF AM29BDD160G Data sheet ( Hoja de datos )

Número de pieza	AM29BDD160G
Descripción	Simultaneous Read/Write Flash Memory
Fabricantes	AMD
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No Preview Available ! Am29BDD160G Data Sheet For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration path for this device. Please refer to the S29CD016G datasheet for specifications and ordering infor- mation. The following document contains information on Spansion memory products. Although the doc-ument is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro-priate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 24960 Revision D Amendment 5 Issue Date June 7, 2006 1 page TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 x16 Mode .................................................................................. 9 x32 Mode .................................................................................. 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11 Table 1. Device Bus Operation .......................................................12 VersatileI/O™ (VIO) Control .................................................... 13 Requirements for Reading Array Data ................................... 13 Simultaneous Read/Write Operations Overview and Restrictions ................................... 13 Overview ............................................................................. 13 Restrictions .......................................................................... 13 Table 2. Bank Assignment for Boot Bank Sector Devices ................................................................................13 Simultaneous Read/Write Operations With Zero Latency ...... 13 Table 3. Top Boot Bank Select .......................................................14 Table 4. Bottom Boot Bank Select ..................................................14 Writing Commands/Command Sequences ............................ 14 Accelerated Program and Erase Operations ....................... 14 Autoselect Functions ........................................................... 14 Automatic Sleep Mode (ASM) ................................................ 14 RESET#: Hardware Reset Pin ............................................... 15 Output Disable Mode .............................................................. 15 Autoselect Mode ..................................................................... 15 Table 5. Am29BDD160 Autoselect Codes (High Voltage Method) .16 Asynchronous Read Operation (Non-Burst) ........................... 16 Figure 1. Asynchronous Read Operation........................................ 16 Synchronous (Burst) Read Operation .................................... 17 Linear Burst Read Operations ................................................ 17 Table 6. 16-Bit and 32-Bit Linear and Burst Data Order .................17 CE# Control in Linear Mode ................................................ 18 ADV# Control In Linear Mode .............................................. 18 RESET# Control in Linear Mode ......................................... 18 OE# Control in Linear Mode ................................................ 18 IND/WAIT# Operation in Linear Mode ................................. 18 Table 7. Valid Configuration Register Bit Definition for IND/WAIT# 20 Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation............................................................................... 20 Burst Access Timing Control ............................................... 21 Initial Burst Access Delay Control ....................................... 21 Table 8. Burst Initial Access Delay ..................................................21 Figure 3. Initial Burst Delay Control ................................................ 21 Configuration Register ............................................................ 22 Table 9. Configuration Register Definitions .....................................22 Table 10. Configuration Register After Device Reset .....................24 Initial Access Delay Configuration .......................................... 24 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . 24 Persistent Sector Protection ................................................... 24 Persistent Protection Bit (PPB) ............................................ 25 Persistent Protection Bit Lock (PPB Lock) .......................... 25 Dynamic Protection Bit (DYB) ............................................. 25 Table 11. Sector Protection Schemes ............................................ 26 Persistent Sector Protection Mode Locking Bit ....................... 26 Password Protection Mode ..................................................... 26 Password and Password Mode Locking Bit ............................ 26 64-bit Password ................................................................... 27 Write Protect (WP#) ................................................................ 27 SecSi™ (Secured Silicon) Sector Protection .......................... 27 SecSi Sector Protection Bit ..................................................... 28 Persistent Protection Bit Lock ................................................. 28 Hardware Data Protection ...................................................... 28 Low VCC Write Inhibit ........................................................... 28 Write Pulse “Glitch” Protection ............................................ 28 Logical Inhibit ....................................................................... 28 Power-Up Write Inhibit ......................................................... 28 VCC and VIO Power-up And Power-down Sequencing ......... 28 Table 12. Sector Addresses for Top Boot Sector Devices ............. 29 Table 13. Sector Addresses for Bottom Boot Sector Devices ........ 30 Table 14. CFI Query Identification String ....................................... 31 Table 15. CFI System Interface String ........................................... 31 Table 16. CFI Device Geometry Definition ..................................... 32 Table 17. CFI Primary Vendor-Specific Extended Query ............... 32 Command Definitions . . . . . . . . . . . . . . . . . . . . . 34 Reading Array Data in Non-burst Mode .................................. 34 Reading Array Data in Burst Mode ......................................... 34 Read/Reset Command ........................................................... 34 Autoselect Command ............................................................. 35 Program Command Sequence ............................................... 35 Accelerated Program Command ............................................ 35 Unlock Bypass Command Sequence ..................................... 35 Figure 4. Program Operation ......................................................... 36 Unlock Bypass Entry Command .......................................... 36 Unlock Bypass Program Command .................................... 36 Unlock Bypass Chip Erase Command ................................ 36 Unlock Bypass CFI Command ............................................ 36 Unlock Bypass Reset Command ......................................... 37 Chip Erase Command ............................................................ 37 Sector Erase Command ......................................................... 37 Figure 5. Erase Operation.............................................................. 38 Sector Erase and Program Suspend Command .................... 38 Sector Erase and Program Suspend Operation Mechanics ... 38 Table 18. Allowed Operations During Erase/Program Suspend ... 38 Sector Erase and Program Resume Command ..................... 39 Configuration Register Read Command ................................. 39 Configuration Register Write Command ................................. 39 Common Flash Interface (CFI) Command .............................. 39 SecSi Sector Entry Command ................................................ 41 Password Program Command ................................................ 41 Password Verify Command .................................................... 41 Password Protection Mode Locking Bit Program Command .. 42 Persistent Sector Protection Mode Locking Bit Program Com- mand ....................................................................................... 42 SecSi Sector Protection Bit Program Command .................... 42 PPB Lock Bit Set Command ................................................... 42 DYB Write Command ............................................................. 42 Password Unlock Command .................................................. 42 PPB Program Command ........................................................ 43 June 7, 2006 Am29BDD160G 3 5 Page PIN CONFIGURATION A–1 = Least significant address bit for the 16-bit data bus, and selects between the high and low word. A –1 is not used for the 32-bit mode (WORD# = VIH). A0–A18 = 19-bit address bus for 16 Mb device. A9 supports 12 V autoselect inputs. DQ0–DQ31 = 32-bit data inputs/outputs/float WORD# = Selects 16-bit or 32-bit mode. When WORD# = VIH, data is output on DQ31–DQ0. When WORD# = VIL, data is output on DQ15–DQ0. CE# = Chip Enable Input. This signal is asynchro- nous relative to CLK for the burst mode. OE# = Output Enable Input. This signal is asyn- chronous relative to CLK for the burst mode. WE# = Write enable. This signal is asynchronous relative to CLK for the burst mode. VSS = Device ground NC = Pin not connected internally RY/BY# = Ready/Busy output and open drain. When RY/BY# = VIH, the device is ready to ac- cept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset oper- ation. LOGIC SYMBOLS x16 Mode 20 A-1 to A18 CLK DQ0–DQ15 CE# OE# WE# RESET# ADV# ACC WP# VIO (VCCQ) WORD# IND/WAIT# RY/BY# 16 CLK ADV# IND# WAIT# WP# ACC VIO (VCCQ) VCC RESET# = Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. = Load Burst Address input. Indicates that the valid address is present on the address inputs. = End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at the data outputs. = Provides data valid feedback only when the burst length is set to continuous. = Write Protect input. When WP# = VOL, the two outermost bootblock sector in the 75% bank are write protected regardless of other sector protection configurations. = Acceleration input. When taken to 12 V, program and erase operations are acceler- ated. When not used for acceleration, ACC = VSS to VCC. = Output Buffer Power Supply (1.65 V to 2.75 V) = Chip Power Supply (2.5 V to 2.75 V) = Hardware reset input x32 Mode 19 A0–A18 CLK DQ0–DQ31 CE# OE# WE# RESET# IND/WAIT# ADV# ACC WP# RY/BY# VIO (VCCQ) WORD# 32 June 7, 2006 Am29BDD160G 9 11 Page

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