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PDF SP5024 Data sheet ( Hoja de datos )
| Número de pieza | SP5024 | |
| Descripción | 3-Wire Bus Controlled Synthesiser | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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1 page  
SP5024
FUNCTIONAL DESCRIPTION
The SP5024 contains all the elements necessary, with the
exception of reference crystal, loop filter and external high
voltage transistor, to control a voltage controlled local oscillator,
so forming a PLL frequency synthesised source.
The system is controlled by a microprocessor via a standard
data, clock, enable, three-wire data bus. The data load
normally consists of a single word, which contains the
frequency and port information, and is only transferred to the
internal data shift register during an enable high period. The
clock input is disabled during enable low periods. New data
words are only accepted by the internal data buffers from the
shift register on a negative transition of the enable, so giving
improved fine tune facility for digital AFC etc.
The data sequence and timing follows the format shown in
Fig. 3.
The frequency is set by loading the programmable divider
with the required 14/15 bit divisor word. The output of this
divider, FPD, is fed to the phase comparator where it is
compared in phase and frequency domain to the internally
generated comparison frequency, FCOMP.
The FCOMP is obtained by dividing the output of an on-chip
crystal controlled oscillator. The crystal frequency used is
generally 4MHz, which gives an FCOMP of 6.25kHz/7.8125kHz
and, when multiplied back up to the synthesised LO, gives a
minimum step size of 50kHz/62.5kHz, respectively.
The programmable divider is preceded by an input RF
preamplifier and high speed, low radiation prescaler. The
preamplifier is arranged to be self oscillating, so giving excellent
input sensitivity. The input sensitivity and impedance are
shown in Figs. 5 and 7, respectively.
The SP5024 contains an improved lock detect circuit
which generates a flag when the loop has attained lock. ‘Out
of lock’ is indicated by high impedance state.
The SP5024 contains 4 general purpose open collector
outputs, ports P1-P4, which are capable of sinking at least
10mA. These outputs are set by the remaining four bits within
the normal data word.
PIN COMPATIBILITY
The SP5024 may be used in SP5510 applications which
require 3-wire bus as opposed to I2C bus data format. In
SP5510 applications where the reference crystal is connected
to pin 3, a small modification is required to ground the crystal
as shown in Fig. 4.
Appropriate connections to the mode select input (pin 3)
must also be made.
In mode 1 (pin 3 'HIGH') the SP5024 is programming and
step size compatible with the Toshiba TD6380, and in mode
2 (pin 3 'LOW') it is compatible with the TD6381. In both
modes a 4MHz crystal is used to derive FCOMP, unlike the
TD6381 which requires a 3.2MHz crystal.
CLOCK
CHIP
ENABLE
DATA
MODE 1 (PIN 3
HIGH)
DATA
MODE 2 (PIN 3
LOW)
217 216 215 214 213 212
P1 P2 P3 P4 MSB
22 21 20
LSB
FREQUENCY DATA (LSB = 62.5kHz, with 4MHz reference)
218 217 216 215 214 213
P1 P2 P3 P4 MSB
22 21 20
LSB
FREQUENCY DATA (LSB = 50kHz, with 4MHz reference)
CLOCK
CHIP
ENABLE
DATA
4
t1
t4 t2
t3
t5
Fig. 3 Data format and timing
t1 = ENABLE SET-UP TIME
t2 = DATA SET-UP TIME
t3 = DATA HOLD TIME
t4 = CLOCK-TO ENABLE TIME
t5 = ENABLE HOLD TIME
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SP5024.PDF ] | |
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