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PDF A8291 Data sheet ( Hoja de datos )
| Número de pieza | A8291 | |
| Descripción | Single LNB Supply and Control Voltage Regulator | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A8291
Single LNB Supply and Control Voltage Regulator
Features and Benefits
▪ 2-wire serial I2C™ -compatible interface: control (write) and
status (read)
▪ LNB voltages (16 programmable levels) compatible with
all common standards
▪ Tracking switch-mode power converter for lowest dissipation
▪ Integrated converter switches and current sensing
▪ Provides up to 500 mA load current
▪ Static current limit circuit allows full current at startup and
13→18V output transition; reliably starts wide load range
▪ Push-pull output stage minimizes 13→18V and 18→13V
output transition times for highly capacitive loads
▪ Adjustable rise/fall time via external timing capacitor
▪ Built-in tone oscillator, factory-trimmed to 22 kHz
facilitates DiSEqC™ tone encoding, even at no-load
▪ Four methods of 22 kHz tone generation, via I2C™ data
bits and/or external pin
▪ Filter bypass MOSFET minimizes losses during tone transmit
▪ 22 kHz tone detector facilitates DiSEqC™ 2.0 decoding
▪ Auxiliary modulation input
▪ LNB overcurrent with timer
▪ Diagnostics for output voltage level, input supply UVLO,
and DiSEqC™ tone output
▪ Cable disconnect diagnostic
Package:
28 pin 5 mm × 5mm MLP/QFN
(suffix ET)
Description
Intended for analog and digital satellite receivers, this single
low noise block converter regulator (LNBR) is a monolithic
linear and switching voltage regulator, specifically designed to
provide the power and the interface signals to an LNB down
converter via coaxial cable. The A8291 requires few external
components, with the boost switch and compensation circuitry
integrated inside of the device. A high switching frequency is
chosen to minimize the size of the passive filtering components,
further assisting in cost reduction.The high levels of component
integration ensure extremely low noise and ripple figures.
The A8291 has been designed for high efficiency, utilizing
the Allegro® advanced BCD process. The integrated boost
switch has been optimized to minimize both switching and
static losses. To further enhance efficiency, the voltage drop
across the tracking regulator has been minimized.
The A8291 has integrated tone detection capability, to support
full two-way DiSEqC™ communications. Several schemes
are available for generating tone signals, all the way down
to no-load, and using either the internal clock or an external
Continued on the next page…
VS
VREG
C3
220 nF
VDD
R1 R2 R3 R4 R5 R6
EXTM
BFC
TDO
SDA
SCL
ADD
IRQ
8291-DS, Rev.3
C1
100 nF
Regulator
DAC
I2 C™-
Compatible
Interface
Functional Block Diagram
L1
33 μH
D1
L3
1 MH
C2
100 μF
VIN
C5
100 μF
LX GNDLX
C6
1 μF
C4
100 nF
BOOST VCP
Charge BFC
Pump
R10 B
17
Boost
Converter
VPump
fsw
LNB
Voltage
Control
EXTM
TMode
Wave
Shape
Linear
Stage
TCAP
Fault Monitor
TGate
fsw
OCP
PNG
TSD
VUV
Clock
Divider 22 kHz
Oscillator
D2
B
BFO
BFI
C12 C
R7
15 7
LNB
C8
D3 220 nF
TCAP
C7
10 nF
L2
220 μH
R9
30 7
C11
0.68 μF
A
PAD GND
TDO
Tone
Detect
TDI R8
100 7
C10
10 nF
D5
B
VOUT
C13
10 nF
C9
220 nF
C
D4
B
A
R9-C11 network is needed only when a highly
inductive load is applied, such as ProBand LNB.
B D2, D4, D5, and R10 are used for surge protection.
C Either C12 or C9 should be used, but not both.
1 page  
A8291
Single LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1
Characteristics
Symbol
Test Conditions
Min.
Bypass FET
Bypass FET Control (BFC) Logic Input
Input Leakage
Bypass FET On Resistance
VBFC(H)
VBFC(L)
IBFCLKG
RDS(on)
ILOAD = 450 mA, and VBFC = Low, or
BFC2 bit = 1
2.0
–
–1
–
Turn On/Off Delay2
Tone
tD(ON/OFF) VBFC = Low, or BFC2 bit = 1
–
Tone Frequency
Tone Amplitude, Peak-to-Peak
Tone Duty Cycle
Tone Rise Time
Tone Fall Time
EXTM Logic Input
EXTM Input Leakage
Tone Detector
fTONE
VTONE(pp)
DCTONE
trTONE
tfTONE
VEXTM(H)
VEXTM(L)
IEXTMLKG
ILOAD = 0 to 450 mA, CLOAD = 750 nF
ILOAD = 0 to 450 mA, CLOAD = 750 nF
ILOAD = 0 to 450 mA, CLOAD = 750 nF
ILOAD = 0 to 450 mA, CLOAD = 750 nF
20
400
40
5
5
2.0
–
–1
Tone Detect Input Amplitude Receive, Peak-to-Peak
Tone Detect Input Amplitude Transmit, Peak-
to-Peak
VTDR(pp)
VTDT(pp)Int
VTDT(pp)Ext
fTONE = 22 kHz sine wave, TMODE = 0
fTONE = 22 kHz sine wave, using internal tone
(options 1 and 2, in figure 1)
fTONE = 22 kHz sine wave, using external
tone (options 3 and 4, in figure 1)
300
400
300
Tone Reject Input Amplitude, Peak-to-Peak
Frequency Capture
Input Impedance2
TDO Output Voltage
TDO Output Leakage
I2C™-Compatible Interface
VTRI(pp)
fTDI
ZTDI
VTDO(L)
ITDOLKG
fTONE = 22 kHz sine wave
600 mVpp sine wave
Tone present, ILOAD = 3 mA
Tone absent, VTDO = 7 V
–
17.6
–
–
–
Logic Input (SDA,SCL) Low Level
Logic Input (SDA,SCL) High Level
Logic Input Hysteresis
Logic Input Current
Logic Output Voltage SDA and IRQ
Logic Output Leakage SDA and IRQ
SCL Clock Frequency
Output Fall Time
Bus Free Time Between Stop/Start
Hold Time Start Condition
Setup Time for Start Condition
SCL Low Time
VSCL(L)
VSCL(H)
VI2CIHYS
II2CI
Vt2COut(L)
Vt2CLKG
fCLK
tfI2COut
tBUF
tHD:STA
tSU:STA
tLOW
VI2CI = 0 to 7 V
ILOAD = 3 mA
Vt2COut = 0 to 7 V
Vt2COut(H) to Vt2COut(L)
–
2.0
–
–10
–
–
–
–
1.3
0.6
0.6
1.3
Continued on the next page…
Typ. Max. Units
––
– 0.8
–1
0.5 1
650 –
V
V
μA
Ω
μs
22 24 kHz
620 800 mV
50 60 %
10 15 μs
10 15 μs
––V
– 0.8 V
– 1 μA
– – mV
– – mV
– – mV
– 100 mV
– 26.4 kHz
8.6 – kΩ
– 0.4 V
– 10 μA
–
–
150
<±1.0
–
–
–
–
–
–
–
–
0.8
–
–
10
0.4
10
400
250
–
–
–
–
V
V
mV
μA
V
μA
kHz
ns
μs
μs
μs
μs
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page 
A8291
Single LNB Supply and Control Voltage Regulator
Control Registers (I2C™-Compatible Write Register)
All main functions of the A8291 are controlled through the I2C™-
compatible interface via the 8-bit Control registers. As the A8291
contains numerous control options, it is necessary to have two
control registers. Each register contains up to 6 bits of data (bit
0 to bit 5), followed by 2 bits for the register address (bit 6 and
bit 7). The power-up states for the control functions are all 0s.
The following tables define the control bits for each address
and the settings for output voltage:
Table 2. Control Register Address (I1, I0) = 00
Bit Name
Function
0 VSEL0
1 VSEL1 See table 4, Output Voltage Amplitude Selection
2 VSEL2
0: LNB = Low range
3 VSEL3
1: LNB = High range
0: Overcurrent disable time off
4 ODT
1: Overcurrent disable time on
0: Disable LNB Output
5 ENB
1: Enable LNB Output
6 I0 Address Bit: 0
7 I1 Address Bit: 0
Bit 0 VSEL0 These three bits provide incremental control over the voltage on the LNB output.
Bit 1 VSEL1 The available voltages provide the necessary levels for all the common standards
Bit 2 VSEL2 plus the ability to add line compensation in increments of 333 mV. The voltage
levels are defined in table 4, Output Voltage Amplitude Selection.
Bit 3 VSEL3 Switches between the low level and high level output voltages on the LNB output.
0 selects the low level voltage and 1 selects the high level. The low-level center voltage
is 12.709 V nominal and the high level is 18.042 V nominal. These may be increased
in steps of 333 mV using the VSEL2, VSEL1 and VSEL0 control register bits.
Bit 4 ODT Enables the overcurrent disable timer. When set to 1, and an overcurrent occurs for
longer than the detection time, the LNB output on that channel is disabled. When set
to 0, and an overcurrent occurs, the LNB output will operate in current limit indefi-
nitely. It is highly recommended that the ODT function be enabled at all times.
Bit 5 ENB Enables the LNB output. When set to 1 the LNB output is switched on. When set to
0, the LNB output is disabled.
Bit 6 I0
Address
Bit 7 I1
Address
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet A8291.PDF ] | |
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