ICS1493-17 Datasheet PDF - ICST
Part Number | ICS1493-17 | |
Description | Clock Synthesizer | |
Manufacturers | ICST | |
Logo | ||
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PRELIMINARY INFORMATION
ICS1493-17
Clock Synthesizer for Portable Systems
Description
The ICS1493-17 is a low-power, low-jitter clock
synthesizer designed to replace multiple crystals and
oscillators in portable audio/video systems. The device
generates a 37 MHz processor clock, a 48 MHz USB
clock, a fixed 22.5792 MHz audio clock, a selectable
24.576 MHz or 22.5792 MHz audio clock, and a 27MHz
reference clock for video. Using ICS’ proprietary mix of
analog and digital Phase-Locked Loop (PLL)
technology, the device spreads the frequency spectrum
of the 37 MHz output, reducing the peak amplitude of
by up to 16 dB. An output enable (OE) pin lowers the
chip power consumption while tri-stating all outputs.
Features
• Extremely low operating current (11 mA)
• Packaged in 20-pin QFN (Pb-free)
• Input crystal or clock frequency of 27 MHz
• Output reference frequency of 27 MHz
• Fixed output frequencies of 37 MHz, 48 MHz and
22.5792 MHz
• Selectable output frequency of either 22.5792 MHz
or 24.576 MHz
• Configurable spread spectrum on 37 MHz output
• Operating core voltage of 1.8 V
• Output voltage of 1.8 V or 2.5 V
• Advanced, low-power CMOS process
Block Diagram
SCK
SDATA
IIC
Control
Logic
27 MHz
X1
clock or
crystal input X2
Crystal
Oscillator/
Clock
Buffer
Optional tuning
capacitors
PLL1
(Spread)
VDD
3
PLL2
PLL3
PLL4
5
GND
VDDO
2
OE
37M
48M
22/24M
22M
27M
MDS 1493-17 A
1
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
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PRELIMINARY INFORMATION
ICS1493-17
Clock Synthesizer for Portable Systems
Parameter
Internal Pull-down Resistor
Internal Pull-up Resistor
Symbol Conditions
RPD OE, 48M, 22M,
22/24M, 37M, 27M
RPu SCK, SDATA
Min.
75
100
Typ.
250
500
Max. Units
kΩ
kΩ
AC Electrical Characteristics
Unless stated otherwise, VDDO = 2.5 V ±5%, Ambient Temperature -10°C to +80°C
Parameter
Symbol Conditions
Min. Typ.
Input Frequency
Output Rise Time
Output Fall Time
Output Impedance
Output Clock Duty Cycle
fIN
tOR 20% to 80%, Note 1 0.7
tOF 80% to 20%, Note 1 0.7
RO VO=VDDO/2
33
VDDO/2, 27 MHz,
40
Note 1
27
1.5
1.5
46
50
VDDO/2, Note 1
45 50
Frequency Synthesis Error
All outputs
0
Modulation Rate
30 35
Short Term Jitter
Cycle-to-Cycle
150
Long Term Jitter
27 MHz, n=1000
Long Term Jitter
48 MHz, n=1000
Long Term Jitter
22M and 22/24M,
n=1000
Long Term Jitter
37 MHz non-spread,
n=1000
1.5
Power-up Time
tPU From minimum VDD
to outputs stable
1.5
Output Enable Time
Output Disable Time
Switching Time
22/24M, Note 2
Note 1: Measured with a 5 pF load.
Note 2: Finish from prior cycle to start of new cycle.
Max. Units
MHz
2.2 ns
2.2 ns
68 Ω
60 %
55 %
ppm
40 kHz
300 ps
600 ps
800 ps
1.2 ns
6 ns
3 ms
50 ns
20 ns
100 ns
MDS 1493-17 A
5
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
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Information | Total 11 Pages | |
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Download | [ ICS1493-17.PDF Datasheet ] |
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