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What is ISL12027?

This electronic component, produced by the manufacturer "Intersil Corporation", performs the same function as "Real Time Clock/Calendar".


ISL12027 Datasheet PDF - Intersil Corporation

Part Number ISL12027
Description Real Time Clock/Calendar
Manufacturers Intersil Corporation 
Logo Intersil Corporation Logo 


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Data Sheet
ISL12027, ISL12027A
August 12, 2010
FN8232.8
Real Time Clock/Calendar with EEPROM
The ISL12027 device is a low power real time clock with
timing and crystal compensation, clock/calender, power-fail
indicator, two periodic or polled alarms, intelligent battery
backup switching, CPU Supervisor and integrated 512x8-bit
EEPROM, in 16 Byte per page format.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12027 and ISL12027A Power Control Settings are
different. The ISL12027 uses the Legacy Mode Setting, and
the ISL12027A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12027A. Please refer to“Power Control Operation” on
page 15 for more details. Also, please refer to “I2C
Communications During Battery Backup and LVR Operation”
on page 24 for important details.
Pinouts
ISL12027, ISL12027A
(8 LD TSSOP)
TOP VIEW
VBAT
VDD
X1
X2
1
2
3
4
8 SCL
7 SDA
6 GND
5 RESET
ISL12027, ISL12027A
(8 LD SOIC)
TOP VIEW
X1
X2
RESET
GND
1
2
3
4
8 VDD
7 VBAT
6 SCL
5 SDA
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8-Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• I2C-bus™ Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
I2C-bus™ is a trademark of NXP B.V., BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries
Copyright Intersil Americas Inc. 2005, 2006, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL12027 equivalent
ISL12027, ISL12027A
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
PARAMETER
CONDITIONS
tRPD
tPURST
VRVALID
VDD Detect to RESET LOW
Power-up Reset Time-Out Delay
Minimum VDD for Valid RESET
Output
VRESET ISL12027-4.5A Reset Voltage Level
ISL12027 Reset Voltage Level
ISL12027-3 Reset Voltage Level
ISL12027-2.7A Reset Voltage Level
ISL12027-2.7 Reset Voltage Level
tWDO Watchdog Timer Period
32.768kHz crystal between X1
and X2
tRST
Watchdog Timer Reset Time-Out 32.768kHz crystal between X1
Delay
and X2
tRSP I2C Interface Minimum Restart Time
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature ≤ +75°C
MIN
(Note 16)
TYP
(Note 5)
500
MA
(Note 16)
100 250 400
1.0
UNITS
ns
ms
V
NOTES
13
4.59 4.64 4.69
4.33 4.38 4.43
3.04 3.09 3.14
2.87 2.92 2.97
2.58 2.63 2.68
1.70 1.75 1.801
725 750 775
225 250 275
225 250 275
V
V
V
V
V
s
ms
ms
ms
1.2 µs
>2,000,000
50
Cycles
Years
Serial Interface (I2C) Specifications
SYMBOL
PARAMETER
CONDITIONS
MIN
VIL SDA, and SCL Input Buffer LOW SBIB = 1 (Under VDD mode)
Voltage
-0.3
VIH SDA, and SCL Input Buffer HIGH SBIB = 1 (Under VDD mode)
Voltage
0.7xVDD
Hysteresis SDA and SCL Input Buffer
Hysteresis
SBIB = 1 (Under VDD mode)
0.05xVDD
VOL SDA Output Buffer LOW Voltage IOL = 4mA
ILI Input Leakage Current on SCL
VIN = 5.5V
ILO I/O Leakage Current on SDA
VIN = 5.5V
0
TIMING CHARACTERISTICS
fSCL SCL Frequency
tIN Pulse Width Suppression Time at Any pulse narrower than the max spec
SDA and SCL Inputs
is suppressed.
tAA SCL Falling Edge to SDA Output SCL falling edge crossing 30% of VDD,
Data Valid
until SDA exits the 30% to 70% of VDD
window.
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
tLOW
tHIGH
Clock LOW Time
Clock HIGH Time
Measured at the 30% of VDD crossing.
Measured at the 70% of VDD crossing.
1300
600
TYP MAX UNITS
0.3xVDD
V
VDD + 0.3
V
V
0.4
0.1 10
0.1 10
V
µA
µA
400 kHz
50 ns
900 ns
ns
ns
ns
NOTES
5 FN8232.8
August 12, 2010


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ISL12027 datasheet


1. Real Time Clock / Calendar

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