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PDF CXD1856R Data sheet ( Hoja de datos )
| Número de pieza | CXD1856R | |
| Descripción | MPEG1 Decoder | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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MPEG1 Decoder
CXD1856Q/R
Description
The CXD1856Q/R is a single-chip MPEG1 decoder
with a built-in CD-ROM decoder which allows
decoding of MPEG1 system, video and audio layers.
A built-in CD-ROM decoder enables direct connection
with a CD-DSP. Combining this chip with a control
microcomputer and 4-Mbit DRAM, etc. allows
configuration of a MPEG1 decoding system for video
CD players, etc.
Features
• Supply voltage: 3.3 ± 0.3V
• Input and output voltages: LVTTL compatible
• 5V can be applied as the input voltage (excluding
some pins)
• Allows decoding of MPEG1 system, video and
audio layers
• Built-in CD-ROM decoder allows direct connection
with a CD-DSP
• CD-ROM decoded output can be transferred to
and stored in an external DRAM
• RGB and YCbCr video data output allowed
• Built-in video sync generator
• Audio data output can support various DAC
• Supports various special playback modes
• Video CD PAL high resolution still picture can be
decoded with a single 4-Mbit DRAM
• 8-bit parallel and 4-line serial host interfaces
• CD-DA through operation allowed
Block Diagram
120 pin QFP (Plastic) 120 pin LQFP (Plastic)
Structure
Silicon gate CMOS IC
Applications
Video CD players, MPEG1 decoder boards, etc.
CD-DSP
I/F
CD-ROM
Decoder
MPEG
System
Decoder
To each circuit block
MPEG
Audio
Decoder
MPEG
Video
Decoder
Audio
I/F
Host
interface
DRAM
Controler
Video Postprocessor
&
Sync Generator
Video
I/F
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97815-PS
1 page  
CXD1856Q/R
Pin No. Symbol
116 HRW
117 XHIRQ
118 XRST
25 CKEY
26 DTVLD
I/O Description
I
R/W signal input when the host interface operates in parallel mode. Serial
clock input in serial mode.
O
Interrupt request signal output. This pin functions as an open drain, and
should therefore be pulled up.
I
Hardware reset signal input. All operation is initialized by setting this pin
low.
Chroma key signal. While the color specified as the key is output, this pin
O becomes low.
When not used, leave this pin open.
Video data judgement signal.
O
While the image data within the frame memory is output, this pin becomes
high; during the border color output or blanking, low.
When not used, leave this pin open.
–5–
5 Page 
CXD1856Q/R
3-6. Interface for CD Signal Processing LSI
BCKFEDG = 0
BCKI
tBCKI
tBCKI
DATI
LRCI, C2PO
BCKFEDG = 1
BCKI
tSBC1
tHBC1
tHBC2
tBCKI
tBCKI
tSBC2
DATI
LRCI, C2PO
tSBC1
tHBC1
tHBC2
tSBC2
Item
BCKI frequency
BCKI pulse width
DATI setting time (for BCKI)
DATI hold time (for BCKI)
LRCI, C2PO setting time (for BCKI)
LRCI, C2PO hold time (for BCKI)
Symbol
fBCKI
tBCKI
tSBC1
tHBC1
tSBC2
tHBC2
Min.
87
20
20
20
20
Max.
5.7
—
—
—
—
—
Unit Remarks
MHz
ns
ns
ns
ns
ns
– 11 –
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