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PDF CY8C9540 Data sheet ( Hoja de datos )
| Número de pieza | CY8C9540 | |
| Descripción | (CY8C9520 - CY8C9560) I/O Expander | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Cypress Semiconductor
CY8C9520,
CY8C9540, and CY8C9560
Preliminary Data Sheet
20-, 40-, and 60-Bit I/O Expander with EEPROM
Features
■ I2C™ interface logic electrically compatible with SMBus.
■ Up to 20 (CY8C9520), 40 (CY8C9540) or 60 (CY8C9560)
I/O data pins independently configurable as inputs, outputs,
bi-directional input/outputs or PWM outputs.
■ 4/8/16 PWM sources with 8-bit resolution.
■ Extendable Soft Addressing™ algorithm allowing flexible
I2C-address configuration.
■ Internal 3-/11-/27-Kbyte EEPROM.
■ Storage of user defaults and I/O port settings in the internal
EEPROM.
■ Optional EEPROM Write Disable (WD) input.
■ Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes.
■ Internal power-on reset (POR).
WD EEPROM
User
Settings
Area
User
A vailable
Area
Clocks
32 kHz
24 MHz
1.5 MHz
93.75 kHz
Divider (1-255)
PWM 0
PWM 15
Control
Unit
GPort 0
GPort 1
GPort 2
8 Bit I/O
5 Bit I/O
3 Bit I/O
or A4-A6
4 Bit I/O
or A1-A3, W
GPort 3
8 Bit I/O
GPort 7
8 Bit I/O
SCL
SDA
Vdd
Vss
Pow er-on-Reset
INT
A0
Overview
The CY8C95xx is a multi-port I/O expander with on-board user-
available EEPROM and several PWM outputs. All devices in
this family operate identically but differ in I/O pins, number of
PWMs, and internal EEPROM size.
The CY8C95xx operates as two I2C slave devices. The first
device is a multi-port I/O expander (single I2C address to
access all ports via registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to dis-
able the EEPROM. The EEPROM utilizes 2-byte addressing to
support the 28-Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM
ouputs. The individual data pins can be configured as open
drain/collector, strong drive (10 mA source, 25 mA sink), resis-
tively pulled-up/-down, or high-impedance. The factory default
configuration is pulled-up internally.
The system master writes to the I/O configuration registers via
the I2C bus. Configuration and output register settings can be
stored as user defaults in a dedicated section of the EEPROM.
If user defaults have been stored in EEPROM, they are
restored to the ports at power-up. While this device can share
the bus with SMBus devices, it can only communicate with
I2C-masters.
There is one dedicated pin that is configured as an interrupt out-
put (INT) and can be connected to the interrupt logic of the sys-
tem master. This signal can inform the system master that there
is incoming data on its ports or that the PWM output state was
changed.
The EEPROM is byte-readable and supports byte-by-byte writ-
ing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The con-
figuration registers can also disable EEPROM operations.
The CY8C95xx has one fixed address pin (A0) and up to six
additional pins (A1-A6) which allow up to 128 devices to share a
common two-wire I2C data bus. The Extendable Soft Address-
ing algorithm provides the option to choose the number of pins
needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
Figure 1-1. Top Level Block Diagram
August 17, 2005
© Cypress Semiconductor Corp. 2005 — Document No. 38-12036 Rev. *A
1
1 page  
www.DataSheet4U.com
2. Pinouts and Pin Descriptions
This chapter describes, lists, and illustrates the CY8C95xx device pins and pinout configurations, along with application examples.
2.1 Pinouts
The CY8C95xx device is available in a variety of packages, which are listed and illustrated in the following tables.
2.1.1 28-Pin Part Pinout
Table 2-1. 28-Pin Part Pinout (SSOP)
Pin
No.
Pin Name
1 GPort0_Bit0_PWM3
2 GPort0_Bit1_PWM1
3 GPort0_Bit2_PWM3
4 GPort0_Bit3_PWM1
5 GPort0_Bit4_PWM3
6 GPort0_Bit5_PWM1
7 GPort0_Bit6_PWM3
8 GPort0_Bit7_PWM1
9 VSS
10 I2C Serial Clock (SCL)
11 I2C Serial Data (SDA)
12 GPort2_Bit3_PWM3/A1
13 A0
14 VSS
15 GPort2_Bit2_PWM0/WD
16 INT
17 GPort2_Bit1_PWM0/A2
18 GPort2_Bit0_PWM2/A3
19 XRES
20 GPort1_Bit7_PWM0/A4
21 GPort1_Bit6_PWM2/A5
22 GPort1_Bit5_PWM0/A6
23 GPort1_Bit4_PWM2
24 GPort1_Bit3_PWM0
25 GPort1_Bit2_PWM2
26 GPort1_Bit1_PWM0
27 GPort1_Bit0_PWM2
28 Vdd
Description
Port 0, Bit 0, PWM 3.
Port 0, Bit 1, PWM 1.
Port 0, Bit 2, PWM 3.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 3.
Port 0, Bit 5, PWM 1.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Ground connection.
I2C Clock.
I2C Data.
Port 2, Bit 3, PWM 3, Address 1.
Address 0.
Ground connection.
Port 2, Bit 2, PWM 0, E2 Write Disable.
Port 2, Bit 1, PWM 0, Address 2.
Port 2, Bit 0, PWM 2, Address 3.
Active high external reset with internal pull
down.
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 0, Address 6.
Port 1, Bit 4, PWM 2.
Port 1, Bit 3, PWM 0.
Port 1, Bit 2, PWM 2.
Port 1, Bit 1, PWM 0.
Port 1, Bit 0, PWM 2.
Supply voltage.
CY8C9520 28-Pin Device
GPort0_Bit0_PWM3
GPort0_Bit1_PWM1
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM3
GPort0_Bit5_PWM1
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
Vss
I2CSerialClock (SCL)
I2CSerialClock (SDA)
GPort2_Bit3_PWM3/A1
A0
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
GPort1_Bit0_PWM2
GPort1_Bit1_PWM0
GPort1_Bit2_PWM2
GPort1_Bit3_PWM0
GPort1_Bit4_PWM2
GPort1_Bit5_PWM0/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
XRES
GPort2_Bit0_PWM2/A3
GPort2_Bit1_PWM0/A2
INT
GPort2_Bit2_PWM0/WD
August 17, 2005
Document No. 38-12036 Rev. *A
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3. Register Reference
This chapter lists and describes the registers of the CY8C95xx device, starting with a register map and then detailed descriptions of
register types.
3.1 Register Mapping Table
The register address is auto-incrementing. If the master device
writes or reads data to or from one register and then continues
data transfer in the same I2C transaction, sequential bytes will
be written or read to or from the following registers. For exam-
ple, if the first byte is sent to the Output Port 1 register, then the
next bytes will be written to Output Port 2, Output Port 3, Output
Port 4 etc. The first byte of each write transaction is treated as
the register address.
To read data from a seires of registers, the master device
should write the starting register address byte then perform a
start and series of read transactions. If no address was sent,
reads start from address 0.
To read a specific register address, the master device should
write the register address byte, then perform a start and read
transaction.
See Figure 1-3, “Port Reading and Writing in Multi-Port Device,”
on page 11.
The device’s register mapping is listed in Table 3-1.
Table 3-1. The Device Register Address Map
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
Register
Input Port 0
Input Port 1
Input Port 2
Input Port 3
Input Port 4
Input Port 5
Input Port 6
Input Port 7
Output Port 0
Output Port 1
Output Port 2
Output Port 3
Output Port 4
Output Port 5
Output Port 6
Output Port 7
Interrupt Status Port 0
Interrupt Status Port 1
Interrupt Status Port 2
Default Register
Value
None
None
None
None
None
None
None
None
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
Table 3-1. The Device Register Address Map (continued)
Address
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
Register
Interrupt Status Port 3
Interrupt Status Port 4
Interrupt Status Port 5
Interrupt Status Port 6
Interrupt Status Port 7
Port Select
Interrupt Mask
Select PWM for Port Output
Inversion
Pin Direction - Input/Output
Drive Mode - Pull Up
Drive Mode - Pull Down
Drive Mode - Open Drain High
Drive Mode - Open Drain Low
Drive Mode - Strong
Drive Mode - Slow Strong
Drive Mode - High-Z
Reserved
Reserved
Reserved
Reserved
PWM Select
Config PWM
Period PWM
Pulse Width PWM
Programmable Divider
Enable WDE, EEE, EERO
Device ID/Status
Reserved
Command
Default Register
Value
00h
00h
00h
00h
00h
00h
FFh
00h
00h
00h
FFh
00h
00h
00h
00h
00h
00h
None
None
None
None
00h
00h
FFh
80h
FFh
00h
20h/40h/60h
None
00h
August 17, 2005
Document No. 38-12036 Rev. *A
11
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| PDF Descargar | [ Datasheet CY8C9540.PDF ] | |
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