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PDF CS5503 Data sheet ( Hoja de datos )
| Número de pieza | CS5503 | |
| Descripción | (CS5501 / CS5503) Measurement A/D Converter | |
| Fabricantes | Crystal | |
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CS5501
CS5503
Low-Cost, 16 & 20-Bit Measurement A/D Converter
Features
l Monolithic CMOS ADC with Filtering
- 6-Pole, Low-Pass Gaussian Filter
l Up to 4 kHz Output Word Rates
- On Chip Self-Calibration Circuitry
- Linearity Error: ±0.0003%
- Differential Nonlinearity:
CS5501: 16-Bit No Missing Codes
(DNL ±1/8 LSB)
CS5503: 20-Bit No Missing Codes
l System Calibration Capability
l Flexible Serial Communications Port
- µC-Compatible Formats
- 3-State Data and Clock Outputs
- UART Format (CS5501 only)
l Pin-Selectable Unipolar/Bipolar Ranges
l Low Power Consumption: 25 mW
- 10 µW Sleep Mode for Portable Applications
l Evaluation Boards Available
Description
The CS5501 and CS5503 are low-cost CMOS A/D con-
verters ideal for measuring low-frequency signals
representing physical, chemical, and biological process-
es. They utilize charge-balance techniques to achieve
16-bit (CS5501) and 20-bit (CS5503) performance with
up to 4 kHz word rates at very low cost.
The converters continuously sample at a rate set by the
user in the form of either a CMOS clock or a crystal. On-
chip digital filtering processes the data and updates the
output register at up to a 4 kHz rate. The converters’ low-
pass, 6-pole Gaussian response filter is designed to al-
low corner frequency settings from 0.1 Hz to 10 Hz in the
CS5501 and 0.5 Hz to 10 Hz in the CS5503. Thus, each
converter rejects 50 Hz and 60 Hz line frequencies as
well as any noise at spurious frequencies.
The CS5501 and CS5503 include on-chip self-calibra-
tion circuitry which can be initiated at any time or
temperature to insure offset and full-scale errors of typi-
cally less than 1/2 LSB for the CS5501 and less than
4 LSB for the CS5503. The devices can also be applied
in system calibration schemes to null offset and gain er-
rors in the input channel.
Each device’s serial port offers two general purpose
modes of operation for direct interface to shift registers
or synchronous serial ports of industry-standard micro-
controllers. In addition, the CS5501’s serial port offers a
third, UART-compatible mode of asynchronous
communication.
ORDERING INFORMATION
See page 33.
I
BP/UPSLEEP
12 11
Calibration
SRAM
SC1 SC2
4
Calibration
Microcontroller
VREF 10
AIN 9
Charge-Balanced A/D Converter
Analog
6-Pole Gaussian
Modulator Low-Pass Digital Filter
AGND 8
DGND 5
Clock Generator Serial Interface Logic
23
18 16 1 19
CLKOUTCLKIN DRDY CS MODESCLK
13 CAL
14 VA+
7 VA-
15 VD+
6 VD-
20 SDATA
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
MAR ‘95
DS31F2
1
1 page  
DYNAMIC CHARACTERISTICS
Parameter
Sampling Frequency
Output Update Rate
Filter Corner Frequency
Settling Time to +_0.0007% FS (FS Step)
20
Symbol
fs
fout
f-3dB
ts
0
-20
CLKIN = 4 MHz
-40
-60
CLKIN = 2 MHz
-80
-100
-120
CLKIN = 1 MHz
-140
1
10 100
Frequency in Hz
Frequency Response
j2 jω
CS5501/CS5503
Ratio
CLKIN/ 256
CLKIN /1024
CLKIN /409,600
506,880/CLKIN
Units
Hz
Hz
Hz
s
1000
j1
-σ -2
-1
-j1
S1,2 = -1.4667 ± j1.8199
S3,4 = -1.7559 ± j1.0008
S5,6 = -1.8746 ± j0.32276
-j2
S-Domain Pole/Zero Plot (Continuous-Time Representation)
H(x) = [1 + 0.694x2 + 0.241x4 + 0.0557x6 + 0.009664x8 + 0.00134x10 + 0.000155x12]-1/2
where x = f/f-3dB, f-3dB = CLKIN/409,600, and f is the frequency of interest.
Continuous-Time Representation of 6-Pole Gaussian Filter
DS31F2
5
5 Page 
CS5501/CS5503
GENERAL DESCRIPTION
The CS5501/CS5503 are monolithic CMOS A/D
converters designed specifically for high resolu-
tion measurement of low-frequency signals. Each
device consists of a charge-balance converter (16-
Bit for the CS5501, 20-Bit for the CS5503),
calibration microcontroller with on-chip SRAM,
and serial communications port.
The CS5501/CS5503 A/D converters perform
conversions continuously and update their output
ports after every conversion (unless the serial port
is active). Conversions are performed and the se-
rial port is updated independent of external
control. Both devices are capable of measuring
either unipolar or bipolar input signals, and cali-
bration cycles may be initiated at any time to
ensure measurement accuracy.
The CS5501/CS5503 perform conversions at a
rate determined by the master clock signal. The
master clock can be set by an external clock or
with a crystal connected to the pins of the on-chip
gate oscillator. The master clock frequency deter-
mines:
1. The sample rate of the analog input signal.
2. The corner frequency of the on-chip digital
filter.
3. The output update rate of the serial output port.
The CS5501/CS5503 design includes several self-
calibration modes and several serial port interface
modes to offer users maximum system design
flexiblity.
The Delta-Sigma Conversion Method
The CS5501/CS5503 A/D converters use charge-
balance techniques to achieve low cost, high
resolution measurements. A charge-balance A/D
converter consists of two basic blocks: an analog
modulator and a digital filter. An elementary ex-
ample of a charge-balance A/D converter is a
conventional voltage-to-frequency converter and
counter. The VFC’s 1-bit output conveys infor-
DS31F2
mation in the form of frequency (or duty cycle),
which is then filtered (averaged) by the counter
for higher resolution.
S/H Amp
LP Filter
1-bit
Digital Filter
Comparator
DAC
16-bits
Figure 1. Charge Balance (Delta-Sigma) A/D Converter
The analog modulator of the CS5501/CS5503 is a
multi-order delta-sigma modulator. The modulator
consists of a 1-bit A/D converter (that is, a com-
parator) embedded in an analog feedback loop
with high open loop gain (see Figure 1). The
modulator samples and converts the input at a rate
well above the bandwidth of interest. The 1-bit
output of the comparator is sampled at intervals
based on the clock rate of the part and this infor-
mation (either a 1 or 0) is conveyed to the digital
filter. The digital filter is much more sophisticated
than a simple counter. The filter on the chip has a
6-pole low pass Gaussian response which rolls off
at 120 dB/decade (36 dB/octave). The corner fre-
quency of the digital filter scales with the master
clock frequency. In comparison, VFC’s and dual
slope converters offer (sin x)/x filtering for high
frequency rejection (see Figure 2 for a compari-
son of the characteristics of these two filter types).
When operating from a 1 MHz master clock the
digital filter in the CS5501/CS5503 offers better
than 120 dB rejection of 50 and 60 Hz line fre-
quencies and does not require any type of line
synchronization to achieve this rejection. It should
be noted that the CS5501/CS5503 will update its
output port almost at 1000 times per second when
operating from the 1 MHz clock. This is a much
higher update rate (typically by a factor of at least
50 times) than either VFCs or dual-slope convert-
ers can offer.
For a more detailed discussion on the delta-sigma
modulator see the Application note "Delta-Sigma
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5503.PDF ] | |
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