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PDF AD8197 Data sheet ( Hoja de datos )
| Número de pieza | AD8197 | |
| Descripción | 4:1 HDMI/DVI Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8197 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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4:1 HDMI/DVI Switch with Equalization
AD8197
FEATURES
4 inputs, 1 output HDMI™/DVI links
Enables HDMI 1.3-compliant receiver
Pin-to-pin compatible with the AD8191
4 TMDS® channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 meters at 2.25 Gbps)
Fully buffered unidirectional inputs/outputs
Globally switchable, 50 Ω on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)
4 auxiliary channels per link
Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
Allows switching of DDC bus and 2 additional signals
Multiple channel bundling modes
1× (4:1) HDMI/DVI link switch (default)
2× (8:1) TMDS channel and auxiliary signal switch
1× (16:1) TMDS channel and auxiliary signal switch
Output disable feature
Reduced power dissipation
Removable output termination
Allows building of larger arrays
Two AD8197s support HDMI/DVI dual-link
Standards compatible: HDMI receiver, HDCP, DVI
Serial (I2C® slave) and parallel control interface
100-lead, 14 mm × 14 mm LQFP, Pb-free package
APPLICATIONS
Multiple input displays
Projectors
A/V receivers
Set-top boxes
Advanced television (HDTV) sets
GENERAL DESCRIPTION
The AD8197 is an HDMI/DVI switch featuring equalized
TMDS inputs and pre-emphasized TMDS outputs, ideal for
systems with long cable runs. Outputs can be set to a high
impedance state to reduce the power dissipation and/or to allow
the construction of larger arrays using the wire-OR technique.
Flexible channel bundling modes (for both the TMDS channels
and the auxiliary signals) allow the AD8197 to be configured as a
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
PARALLEL
SERIAL
I2C_SDA
I2C_SCL
I2C_ADDR[2:0]
VTTI
3
22
CONFIG
INTERFACE
RESET
CONTROL
LOGIC
AD8197
AVCC
DVCC
AMUXVCC
AVEE
DVEE
IP_A[3:0] +
IN_A[3:0] –
IP_B[3:0] +
IN_B[3:0] –
IP_C[3:0] +
IN_C[3:0] –
IP_D[3:0] +
IN_D[3:0] –
4
4
4
4
4
4 EQ
4
4
SWITCH
CORE
PE
4
4
HIGH SPEED BUFFERED
VTTO
+ OP[3:0]
– ON[3:0]
VTTI
AUX_A[3:0]
AUX_B[3:0]
AUX_C[3:0]
AUX_D[3:0]
4
4
4
SWITCH
CORE
4
4
LOW SPEED UNBUFFERED
BIDIRECTIONAL
AUX_COM[3:0]
Figure 1.
TYPICAL APPLICATION
MEDIA CENTER
HDTV SET
GAME CONSOLE
SET-TOP BOX
HDMI
RECEIVER
AD8197
DVD PLAYER
04:20
Figure 2. Typical HDTV Application
4:1 single HDMI/DVI link switch, a dual 8:1 switch, or a single
16:1 switch.
The AD8197 is provided in a 100-lead LQFP, Pb-free, surface-
mount package, specified to operate over the −40°C to +85°C
temperature range.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats, and greater than
UXGA (1600 × 1200) DVI resolutions.
2. Input cable equalizer enables use of long cables at the input
(more than 20 meters of 24 AWG cable at 2.25 Gbps).
3. Auxiliary switch routes a DDC bus and two additional signals
for a single-chip, HDMI 1.3 receive-compliant solution.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD8197
Parameter
SERIAL CONTROL INTERFACE5
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
PARALLEL CONTROL INTERFACE
Input High Voltage, VIH
Input Low Voltage, VIL
Conditions/Comments
Min
Typ Max
Unit
2V
0.8 V
2.4 V
0.4 V
2V
0.8 V
1 Differential interpair skew is measured between the TMDS pairs of a single link.
2 AD8197 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
4 Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI links are deactivated. Minimum and
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.
5 The AD8197 is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 32
5 Page 
AD8197
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
HDMI CABLE
DIGITAL
PATTERN
GENERATOR
AD8197
EVALUATION
BOARD
SERIAL DATA
ANALYZER
REFERENCE EYE DIAGRAM AT TP1
SMA COAX CABLE
TP1 TP2
Figure 9. Test Circuit Diagram for TX Eye Diagrams
TP3
0.125UI/DIV AT 2.25Gbps
Figure 10. TX Eye Diagram at TP2, PE = 2 dB
0.125UI/DIV AT 2.25Gbps
Figure 12. TX Eye Diagram at TP3, PE = 2 dB (Cable = 2 meters, 30 AWG)
0.125UI/DIV AT 2.25Gbps
Figure 11. TX Eye Diagram at TP2, PE = 6 dB
0.125UI/DIV AT 2.25Gbps
Figure 13. TX Diagram at TP3, PE = 6 dB (Cable = 10 meters, 28 AWG)
Rev. 0 | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD8197.PDF ] | |
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