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PDF AM29F800B Data sheet ( Hoja de datos )
| Número de pieza | AM29F800B | |
| Descripción | Sector Erase Flash Memory | |
| Fabricantes | AMD | |
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PRELIMINARY
Am29F800T/Am29F800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS
5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s Package options
— 44-pin SO
— 48-pin TSOP
s Minimum 100,000 write/erase cycles guaranteed
s High performance
— 70 ns maximum access time
s Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
fifteen 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
s Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
s Embedded Erase Algorithm
— Automatically pre-programs and erases the chip
or any sector
GENERAL DESCRIPTION
The Am29F800 is an 8 Mbit, 5.0 Volt-only Flash mem-
ory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase capability, the 8 Mbits
of data are divided into 19 sectors as follows: one 16
Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte.
Eight bits of data appear on DQ0–DQ7 in byte mode; in
word mode 16 bits appear on DQ0–DQ15. The
Am29F800 is offered in 44-pin SO and 48-pin TSOP
packages. This device is designed to be programmed
in-system with the standard system 5.0 Volt VCC sup-
ply. A VPP of 12.0 volts is not required for program or
erase operations. The device can also be programmed
in standard EPROM programmers.
8/18/97
s Embedded Program Algorithm
— Automatically programs and verifies data at
specified address
s Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
s Erase Suspend/Resume
— Supports reading data from or programming
data to a sector not being erased
s Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
s Enhanced power management for standby
mode
— 1 µA typical standby current
s Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
s Hardware RESET pin
— Resets internal state machine to the read mode
The standard Am29F800 offers access times of 70 ns, 90
ns, 120 ns, and 150 ns, allowing high-speed micropro-
cessors to operate without wait states. To eliminate bus
contention, the device has separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The Am29F800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
controls the erase and program circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
Publication# 20375 Rev: C Amendment/+1
Issue Date: August 1997
1 page  
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PRELIMINARY
Standard TSOP
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse TSOP
48 A16
47 BYTE
46 VSS
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE
27 VSS
26 CE
25 A0
20375C-3
48 A15
47 A14
46 A13
45 A12
44 A11
43 A10
42 A9
41 A8
40 NC
39 NC
38 WE
37 RESET
36 NC
35 NC
34 RY/BY
33 A18
32 A17
31 A7
30 A6
29 A5
28 A4
27 A3
26 A2
25 A1
20375C-4
8/18/97
Am29F800T/Am29F800B
5
5 Page 
PRELIMINARY
Table 6. Sector Address Tables (Am29F800B)
A18 A17 A16 A15 A14 A13 A12
Sector
Size
(x16)
(x8)
Address Range Address Range
16 Kbytes
SA0 0 0 0 0 0 0 X
00000h–01FFFh 00000h–03FFFh
8 Kwords
8 Kbytes
SA1 0 0 0 0 0 1 0
02000h–02FFFh 04000h–05FFFh
4 Kwords
8 Kbytes
SA2 0 0 0 0 0 1 1
03000h–03FFFh 06000h–07FFFh
4 Kwords
32 Kbytes
SA3 0 0 0 0 1 X X
04000h–07FFFh 08000h–0FFFFh
16 Kwords
64 Kbytes
SA4 0 0 0 1 X X X
08000h–0FFFFh 10000h–1FFFFh
32 Kwords
64 Kbytes
SA5 0 0 1 0 X X X
10000h–17FFFh 20000h–2FFFFh
32 Kwords
64 Kbytes
SA6 0 0 1 1 X X X
18000h–1FFFFh 30000h–3FFFFh
32 Kwords
64 Kbytes
SA7 0 1 0 0 X X X
20000h–27FFFh 40000h–4FFFFh
32 Kwords
64 Kbytes
SA8 0 1 0 1 X X X
28000h–2FFFFh 50000h–5FFFFh
32 Kwords
64 Kbytes
SA9 0 1 1 0 X X X
30000h–37FFFh 60000h–6FFFFh
32 Kwords
64 Kbytes
SA10 0 1 1 1 X X X
38000h–3FFFFh 70000h–7FFFFh
32 Kwords
64 Kbytes
SA11
1
0
0
0
X
X
X
40000h–47FFFh 80000h–8FFFFh
32 Kwords
64 Kbytes
SA12 1 0 0 1 X X X
48000h–4FFFFh 90000h–9FFFFh
32 Kwords
64 Kbytes
SA13 1 0 1 0 X X X
50000h–57FFFh A0000h–AFFFFh
32 Kwords
64 Kbytes
SA14 1 0 1 1 X X X
58000h–5FFFFh B0000h–BFFFFh
32 Kwords
64 Kbytes
SA15 1 1 0 0 X X X
60000h–67FFFh C0000h–CFFFFh
32 Kwords
64 Kbytes
SA16 1 1 0 1 X X X
68000h–6FFFFh D0000h–DFFFFh
32 Kwords
64 Kbytes
SA17 1 1 1 0 X X X
70000h–77FFFh E0000h–EFFFFh
32 Kwords
64 Kbytes
SA18 1 1 1 1 X X X
78000h–7FFFFh F0000h–FFFFFh
32 Kwords
Note: The address range is A18:A–1 if in byte mode (BYTE = VIL). The address range is A18:A0 if in word mode (BYTE = VIH).
8/18/97
Am29F800T/Am29F800B
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM29F800B.PDF ] | |
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