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PDF CY7B995 Data sheet ( Hoja de datos )
| Número de pieza | CY7B995 | |
| Descripción | High-Speed Multi-Phase PLL Clock Buffer | |
| Fabricantes | Cypress Semiconductor | |
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CY7B995
2.5/3.3V 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
Features
Description
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 100 ps
• Cycle-cycle jitter <100 ps
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50Ω terminated lines
• LVCMOS/LVTTL over-voltage tolerant reference input
• Selectable phase-locked loop (PLL) frequency range
and lock indicator
• Phase adjustments in 625/1250 ps steps up to ± 7.5 ns
• (1-6,8,10,12) x multiply and (1/2,1/4)x divide ratios
• Spread-Spectrum-compatible
• Power-down mode
• Selectable reference divider
• Industrial temperature range: -40°C to +85°C
• 44-pin TQFP package
The CY7B995 RoboClock is a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program both the frequency and the phase of the
output banks through nF[0:1] and DS[0:1] pins. The adjustable
phase feature allows the user to skew the outputs to lead or
lag the reference clock. Any one of the outputs can be con-
nected to feedback input to achieve different reference fre-
quency multiplication and divide ratios and zero input-output
delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin con-
trols the synchronization of the output signals to either the ris-
ing or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA
(3.3V).
Block Diagram
PD#/DIV
REF
FB
DS1:0
1F1:0
TEST PE/HD FS VDDQ1
3
/R
/N
33
33
PLL
3
3
Phase
3 Select
2F1:0
3F1:0
4F1:0
3
Phase
3 Select
3 Phase
3
Select
and /K
3 Phase
3
Select
and /M
Pin Configuration
LOCK
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
VDDQ3
4Q0
4Q1
4F1
sOE#
PD#/DIV
PE/HD
VDDQ4
VDDQ4
4Q1
4Q0
VSS
VSS
VSS
1 44 43 42 41 40 39 38 37 36 35 3433
2 32
3 31
4 30
5 29
6
CY7B995
28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
1F0
DS1
DS0
LOCK
VDDQ1
VDDQ1
1Q0
1Q1
VSS
VSS
VSS
VDDQ4 sOE#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07337 Rev. *A
Revised February 24, 2004
1 page  
CY7B995
.DC Specifications @ 2.5V
Parameter
Description
Conditions
Min. Max.
VDD
VIL
VIH
VIHH[11]
VIMM[11]
VILL[11]
IIL
I3
2.5 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
2.5V ± 5%
REF, FB and sOE# Inputs
Input HIGH Voltage
Input MID Voltage
3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV,
PE/HD). (These pins are normally wired to VDD, GND, or
unconnected)
Input LOW Voltage
Input Leakage Current VIN = VDD/GND,VDD = Max; (REF and FB inputs)
HIGH, VIN = VDD
3-Level Input DC Current MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
2.375
–
1.7
VDD –
–0.4
VDD/2
– 0.2
–
–5
–
–50
–200
2.625
0.7
–
–
VDD/2
+ 0.2
0.4
5
200
50
–
IPU
IPD
VOL
VOH
IDDQ
Input Pull-Up Current
VIN = VSS, VDD = Max
Input Pull-Down Current VIN = VDD, VDD = Max, (sOE#)
IOL = 12mA (PE/HD = L/H), (nQ[0:1])
Output LOW Voltage
IOL = 20mA (PE/HD = MID),(nQ[0:1])
IOL = 2mA (LOCK)
IOH = –12mA (PE/HD = L/H),(nQ[0:1])
Output HIGH Voltage
IOH = –20mA (PE/HD = MID),(nQ[0:1])
IOH = –2mA (LOCK)
Quiescent Supply Current
VDD = Max, TEST = MID, REF = LOW, sOE# = LOW,
Outputs not loaded
–25 –
– 100
– 0.4
– 0.4
0.4
2.0 –
2.0 –
2.0
–2
IDDPD
IDD
CIN
Power-down Current
Dynamic Supply Current
Input Pin Capacitance
PD#/DIV, sOE# = LOW
Test,nF[1:0],DS[1:0] = HIGH; VDD = Max
@100MHz
10(typ.) 25
150
4
Unit
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
mA
µA
mA
pF
DC Specifications @ 3.3V
Parameter
Description
Condition
Min.
Max.
VDD
VIL
VIH
VIHH[11]
VIMM[11]
VILL[11]
IIL
3.3 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
Input Leakage Current
3.3V ± 10%
2.97 3.63
REF, FB and sOE# Inputs
– 0.8
2.0 –
3-Level Inputs
VDD– –0.6
–
(TEST, FS, nF[1:0], DS[1:0],PD#/DIV,
PE/HD); (These pins are normally
VDD/2 – 0.3
VDD/2 + 0.3
wired to VDD,GND or unconected
–
0.6
VIN = VDD/GND,VDD = Max
(REF and FB inputs)
–5 5
HIGH, VIN = VDD
MID, VIN = VDD/2
3-Level
Inputs,
(TEST, FS,
–
–50
200
50
I3 3-Level Input DC Current
nF[1:0],
LOW, VIN = VSS
DS[1:0],
PD#/DIV,
–200
–
PE/HD)
IPU Input Pull-Up Current
VIN = VSS, VDD = Max
–25
IPD Input Pull-Down Current
VIN = VDD, VDD = Max, (sOE#)
–
Note:
11. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
–
100
Unit
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
Document #: 38-07337 Rev. *A
Page 5 of 11
5 Page 
CY7B995
Document History Page
Document Title:CY7B995 Roboclock® 2.5/3.3V 200-MHz High-speed Multi-phase PLL Clock Buffer
Document Number: 38-07337
REV.
ECN No. Issue Date
Orig. of
Change
Description of Change
** 122626 01/10/03
RGL
New Data Sheet
*A 205743 See ECN
RGL
Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin
29 from VDD to VDDQ1
Added pin 1 indicator in the Pin Configuration Drawing
Document #: 38-07337 Rev. *A
Page 11 of 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CY7B995.PDF ] | |
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