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PDF 74ACT74 Data sheet ( Hoja de datos )

Número de pieza 74ACT74
Descripción DUAL D-TYPE FLIP FLOP
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! 74ACT74 Hoja de datos, Descripción, Manual

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74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
fMAX = 250MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
s 50TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
transition of the clock pulse.
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT74B
74ACT74M
T&R
74ACT74MTR
74ACT74TTR
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/12

1 page




74ACT74 pdf
74ACT74
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0
3
pF
CPD Power Dissipation
Capacitance (note 5.0
1)
fIN = 10MHz
43
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per
Flip-Flop)
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500or equivalent
RT = ZOUT of pulse generator (typically 50)
5/12

5 Page





74ACT74 arduino
DIM.
A
A1
A2
b
c
D
E
E1
e
K
L
74ACT74
MIN.
0.05
0.85
0.19
0.09
4.9
6.25
4.3
0o
0.50
TSSOP14 MECHANICAL DATA
mm
TYP.
0.10
0.9
5
6.4
4.4
0.65 BSC
4o
0.60
MAX.
1.1
0.15
0.95
0.30
0.20
5.1
6.5
4.48
8o
0.70
MIN.
0.002
0.335
0.0075
0.0035
0.193
0.246
0.169
0o
0.020
inch
TYP.
0.004
0.354
0.197
0.252
0.173
0.0256 BSC
4o
0.024
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.201
0.256
0.176
8o
0.028
A A2
A1 b
e
D
c
KL
E
PIN 1 IDENTIFICATION
1
E1
11/12

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