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PDF AN1672D Data sheet ( Hoja de datos )
| Número de pieza | AN1672D | |
| Descripción | The ECL Translator Guide | |
| Fabricantes | ON Semiconductor | |
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AN1672/D
The ECL Translator Guide
PECL • LVPECL • NECL • TTL •
LVTTL/LVCMOS • CMOS
Prepared by: Paul Shockman
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Objective
This application note is intended to provide the basic
device selection and connection information to enable signal
translation interface between ON Semiconductor’s ECL
logic operating in various supply modes This document also
provides information regarding translation between our
ECL devices and TTL (5 V), CMOS (5 V), or
LVTTL/LVCMOS (3.3 V) devices. For translation interface
with LVDS, see AN1568.
Translation to and from ECL technology is discussed in
three section divisions:
Section 1. Translation between differently supplied
ECL drivers and receivers
Section 2. Translation from different ECL operating
mode drivers to non ECL receivers
Section 3. Translation from non ECL drivers to
different ECL operating mode receivers
Proper translation occurs when the driver’s output logic
levels are within the spec limits of the receiver and are
recognized. Specific device data sheets should be consulted
for exact specifications and parameter limits.
Resources
IBIS and SPICE models may be found at
www.onsemi.com for most devices. General ECL
information, also online, may be consulted such as
AND8020, AND8066, and AND8072.
General Background
TTL and CMOS drivers generally source current (to the
receiver) in the HIGH state and sink current (from the
receiver) in the LOW state. In contrast, ECL drivers source
current in both HIGH and LOW states (to the receiver).
Receiver inputs do not require any “termination” although
any driver may or may not require termination
considerations. The driver termination considerations may
be located physically near or internal to a receiver.
TTL and CMOS devices will usually be operated across
a single positive power supply (VCC or VDD) and ground.
ECL devices may operate similarly across a single Positive
supply and VEE (Ground) as Positive ECL (PECL) or Low
Voltage Positive ECL (LVPECL). Or traditionally, ECL
devices may span across Ground and a single negative
power supply, VEE, as Negative ECL (NECL) or Low
Voltage Negative ECL (LVNECL). Any device may be
operated with all pins offset by a fixed voltage, but interface
with standard levels may require a translation device. A pure
ECL device might be operated in NECL, PECL, or LVPECL
mode by simply shifting all voltage levels. Of course, a
translator dedicated to a specific technology will expect only
fixed voltages and can’t usually operate in different, or
shifted voltage modes.
© Semiconductor Components Industries, LLC, 2004
November, 2004 − Rev. 9
1
Publication Order Number:
AN1672/D
1 page  
AN1672/D
Typical drive current strength of the TTL output is shown in the following two tables, Table 5 and Table 6, and their graphs,
Figure 1 and Figure 2.
Table 5. ELT TTL Series Drive LOW Current (IOL) vs
Voltage (VOL)
IOL
0.010
VOL
0.162
0.020
0.209
0.030
0.256
0.040
0.303
0.079
0.465
0.118
0.628
0.12
0.10
0.08
0.06
0.04
0.02
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL (V)
Figure 1. ELT TTL Series Drive LOW Current (IOL)
versus Voltage (VOL)
Table 6. ELT Series TTL Drive HIGH Current (IOH) vs
Voltage (VOH)
IOH
−0.0379
VOH
2
−0.0316
2.26
−0.0249
2.508
−0.0164
2.9
−0.0091
3.167
−0.0031
3.339
−0.001
3.4
Typical ELT TTL series output impedance in the HIGH
state is about 43 W. In the LOW state output impedance is
about 42 W.
Typical tPLH and tPHL may differ as much as 0.5 ns. At
higher frequencies, the output swing will decrease. Gain is
typically about five and inputs require a minimum of
200 mVpp swing. Jitter is typically 500 ps. Measurements
are made at 1.5 V for AC characteristics such as tpd and
skew.
From PECL to LVTTL
This translation requires two devices for a direct, active
connection. First, a level shift from PECL to LVPECL is
done with the MC100LVEL92. Then, a translation from
LVPECL to LVTTL is done with either the LVELT23,
EPT21, EPT23, LVELT23, or EPT26 (see segment below).
No sequencing is needed in powering up the
MC100LVEL92, although both Positive supply levels, VCC
and LVCC, must be connected for proper operation.
−0.04
−0.03
−0.02
−0.01
0
2 2.5 3 3.5
VOH (V)
Figure 2. ELT Series TTL Drive HIGH Current (IOH)
versus Voltage (VOL)
From PECL to CMOS
The translation from PECL to CMOS is accomplished
through two stages, from PECL to an intermediary stage
(such as either TTL or LVTTL), then from the intermediary
stage to CMOS. When the intermediary stage is through
TTL, then the final stage will be from TTL to CMOS using
any of the HCT type devices (i.e., MC74HCT245A), or
ACT (i.e., MC74ACT244).
From LVPECL to TTL
Translation from LVPECL to TTL will be similar to
“PECL to LVTTL” and the prior segment should be
reviewed. The input common mode range maximum (2.2 V)
for ELT21 / ELT23 is generally considered to be sufficient
to allow recognition of LVPECL HIGH levels (>2.2 V), thus
allowing proper translation.
http://onsemi.com
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| PDF Descargar | [ Datasheet AN1672D.PDF ] | |
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