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PDF MAX7472 Data sheet ( Hoja de datos )
| Número de pieza | MAX7472 | |
| Descripción | (MAX7472 / MAX7473) HDTV Anti Aliasing Filters | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX7472 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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19-0619; Rev 0; 8/06
EVAALVUAAILTAIOBNLEKIT
HDTV Anti-Aliasing Filters with Triple-Input Mux
General Description
The MAX7472/MAX7473 triple-channel anti-aliasing fil-
ters and buffers with triple-input mux are ideal for high-
definition (HD) and standard-definition (SD) television
(TV) applications. Compatible with 1080i, 720p, 480p,
and 480i scanning system standards as well as com-
puter format signals, the MAX7472/MAX7473 support
component video (Y PB PR, GsBR, and RGBHV) as well
as composite (CVBS) and S-video (Y/C).
The MAX7472/MAX7473 limit the input bandwidth for
anti-aliasing and out-of-band noise reduction prior to
digital conversion by an ADC or video decoder. The
frequency response of the MAX7472/MAX7473 can be
continuously varied in 256 linear steps from below SD
response to beyond HD response through an I2C† inter-
face. The adjustable cutoff frequency allows filter opti-
mization for sampling rate and noise reduction. The
MAX7472/MAX7473 also include 3:1 multiplexers for
selection of three complete sets of video inputs through
the I2C interface.
The MAX7472/MAX7473 drive a 2VP-P video signal into
a standard 150Ω load. The inputs are AC-coupled and
the outputs can be either DC- or AC-coupled. The
MAX7472 has a gain of 0dB and the MAX7473 has a
gain of +6dB. Both devices are available in a 28-pin
TQFN package and are fully specified over the upper-
commercial (0°C to +85°C) temperature range.
HDTV (LCD, PDP, DLP, CRT)
Set-Top Boxes
Personal Video Recorders
Home Theaters
Applications
Features
o Continuously Variable Anti-Aliasing Filter
5MHz to 34MHz in 256 Steps
o 3:1 Input Mux on Each Video Filter
o Supports All Standard Video and Computer Input
Formats
480i, 480p, 720p, 1080i
QVGA, VGA, SVGA, XGA, SXGA, UXGA
Y PB PR, GsBR, RGBHV, Y/C, CVBS
o Accepts Any Input Sync Format
Sync on Y, Sync on G, External Sync
(Positive or Negative)
Sync on All Channels
o Buffered Outputs Drive Standard 150Ω Video Load
0dB (MAX7472)
+6dB (MAX7473)
o DC- or AC-Coupled Outputs
o Single +5V Analog and +3.3V Digital Supplies
o 5mW Power-Down Mode
o Lead (Pb)-Free 28-Pin TQFN Package
Ordering Information
PART
PIN-PACKAGE
PKG CODE
BUFFER
GAIN (dB)
MAX7472UTI+ 28 TQFN-EP*
T2855-8
0
MAX7473UTI+** 28 TQFN-EP*
T2855-8
+6
Note: All devices are specified over the 0°C to +85°C operat-
ing temperature range.
+Indicates lead-free packaging.
*EP = Exposed pad.
**Future product—contact factory for availability.
Pin Configuration
Typical Operating Circuit appears at end of data sheet.
†Purchase of I2C components from Maxim Integrated
Products, Inc., or one of its sublicensed Associated
Companies, conveys a license under the Philips I2C Patent
Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as
defined by Philips.
TOP VIEW
21 20 19 18 17 16 15
AVDD 22
A0 23
A1 24
AGND 25
AGND 26
MAX7472
MAX7473
INA1 27
INB1 28
+
EP*
14 SCL
13 SYNCC
12 SYNCB
11 SYNCA
10 DGND
9 INC3
8 INB3
1 234567
TQFN
5mm x 5mm
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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HDTV Anti-Aliasing Filters with Triple-Input Mux
Typical Operating Characteristics
(AVDD = +5V, DVDD = 3.3V, RLOAD = 150Ω to GND, CIN = 0.1µF, TA = +25°C.)
FREQUENCY RESPONSE (MAX7472)
10
0
-10
CODE 40
-20
-30
CODE 90
-40
CODE 220
CODE 255
-50
-60
-70
-80
0.1
1 10 100
FREQUENCY (MHz)
1000
PASSBAND FLATNESS (MAX7473)
7.0
6.5
6.0
CODE 40
5.5
5.0 CODE 90
4.5
4.0 CODE 220
3.5 CODE 255
3.0
0.1
1 10
FREQUENCY (MHz)
100
FREQUENCY RESPONSE (MAX7473)
10
0
-10
CODE 40
-20
CODE 220
-30 CODE 255
-40 CODE 90
-50
-60
-70
0.1
1 10 100
FREQUENCY (MHz)
1000
90
80
70
60
50
40
30
20
10
0
0.1
GROUP DELAY
SD
HD
1 10
FREQUENCY (MHz)
100
PASSBAND FLATNESS (MAX7472)
1.0
0.5
0
-0.5 CODE 40
-1.0
CODE 90
-1.5
-2.0 CODE 220
-2.5 CODE 255
-3.0
0.1
1 10
FREQUENCY (MHz)
100
2T RESPONSE (1 IRE = 7.14mV)
100ns/div
MODULATED 12.5T RESPONSE
400ns/div
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0.2
0.1
0
-0.1
-0.2
1
DIFFERENTIAL GAIN
DIFFERENTIAL PHASE
23456
7
-3dB FREQUENCY vs. CONTROL CODE
35
30
25
20
15
10
5
0 51 102 153 204 255
CONTROL CODE
_______________________________________________________________________________________ 5
5 Page 
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HDTV Anti-Aliasing Filters with Triple-Input Mux
tion). After receiving the proper address, the
MAX7472/MAX7473 (slave) issue an ACK by pulling
SDA low for one clock cycle.
The MAX7472/MAX7473 slave address consists of 5
fixed bits A6–A2 (set to 10010) followed by 2 pin-pro-
grammable bits A1 and A0. The most significant address
bit (A6) is transmitted first, followed by the remaining
bits. Addresses A1 and A0 can also be driven dynami-
cally if required, but the values must be stable when they
are expected in the address sequence.
Command Byte (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (Figure 5)
and a write bit (R/W = 0). After successfully receiving
its address, the MAX7472/MAX7473 (slave) issue an
ACK. The MAX7472/MAX7473 recognize the next byte
after a successfully received address as the command
byte (Table 3).
Use the command byte to configure the MAX7472/
MAX7473. While most of the commands listed in Table
3 modify the functionality of the MAX7472/
MAX7473, some commands prepare the device for fur-
ther data transfers (see the Control/Status Register,
Frequency Register, and Channel-Selection Register
sections.) When the write cycle is prematurely aborted,
the register is not updated. Figures 6 and 7 show
examples of write sequences.
SDA 1
MSB
SCL
0
0
Figure 5. Slave-Address Byte Definition
10
A1 A0 R/W ACK
LSB
SCL
SDA
SDA
DIRECTION
1 0 0 1 0 A1 A0 R/W ACK 0 0 0 1 0 0 1 0 ACK
C7 C6 C5 C4 C3 C2 C1 C0
IN TO MAX7472/MAX7473
OUT
IN OUT
START
SCL (CONT)
SDA (CONT)
F7 F6 F5 F4 F3 F2 F1 F0 ACK
SDA
DIRECTION
IN
OUT IN
COMMAND WORD C7–C0 IS 00010010.
Figure 6. Write Sequence to Update the Frequency Register
STOP
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MAX7472.PDF ] | |
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