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PDF LM8333 Data sheet ( Hoja de datos )
| Número de pieza | LM8333 | |
| Descripción | Keypad Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 2006
LM8333
Keypad Controller with I/O Expansion and ACCESS.bus
Host Interface
1.0 General Description
The LM8333 is a general-purpose controller for matrix-
addressed keypads which provides an ACCESS.bus (I2C-
compatible) interface to a host microcontroller. It offloads the
burden of keyboard scanning from the host, while providing
extremely low power consumption in both operational and
standby modes. It supports keypad matrices up to 8 x 8 in
size (plus another 8 special-function keys), for portable ap-
plications such as cellphones, PDAs, games, and other
handheld applications.
Key press and release events are encoded into a byte format
and loaded into a FIFO buffer for retrieval by the host pro-
cessor. An interrupt output (IRQ) is used to signal events
such as keypad activity, a state change on either of two
interrupt-capable general-purpose I/O pins, or an error con-
dition. Interrupt and error codes are available to the host by
reading dedicated registers.
Four general-purpose I/O pins are available, two of which
have interrupt capability. A pulse-width modulated output
based on a host-programmable internal timer is also avail-
able, which can be used as a general-purpose output if the
PWM function is not required.
To minimize power, the LM8333 automatically enters a low-
power standby mode when there is no keypad, I/O, or host
activity.
The device is packaged in a 49-pin MICRO-ARRAY chip-
scale package.
2.0 Features
n 8 x 8 standard keys
n 8 special function keys (SF keys) providing a total of 72
keys for the maximum keyboard matrix
n ACCESS.bus (I2C-compatible) communication interface
to the host
n Four general purpose host programmable I/O pins with
two optional (slow) external Interrupts
n 16 byte FIFO buffer to store key pressed and key
released events
n Error control with error reports on (FIFO overrun,
Keypad overrun, invalid command)
n Host programmable PWM
n Host programmable active time and debounce time
3.0 Block Diagram
© 2006 National Semiconductor Corporation DS202106
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20210601
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6.0 Typical Application
FIGURE 1. Typical Keypad Configuration
20210603
6.1 I/O EXPANSION OPTIONS
• One host-programmable PWM output which also may be
used as a general-purpose output.
• Four host-programmable general-purpose I/O pins, GE-
N_IO_0, GEN_IO_1, GEN_IO_2, and GEN_IO_3. GE-
N_IO_0 and GEN_IO_1 can also be configured for “slow”
interrupts, in which any transition will trigger a hardware
interrupt event to the host.
6.2 WATCHDOG TIMER
The watchdog timer is always enabled in hardware. To use
the timer, connect the WD_OUT output to the RESET input.
6.3 HALT MODE
The fully static architecture of the LM8333 allows stopping
the internal RC clock in Halt mode, which reduces power
consumption to the minimum level.
Halt mode is entered when no key-press, key-release, or
ACCESS.bus activity is detected for a certain period of time
(by default, 500 milliseconds). The mechanism for entering
Halt mode is always enabled in hardware, but the host can
program the period of inactivity which triggers entry into Halt
mode.
The LM8333 will remain in Active mode as long as a key
event, or any other event, which causes the IRQ output to be
asserted is not resolved.
6.3.1 ACCESS.bus Activity
When the LM8333 is in Halt mode, any activity on the
ACCESS.bus interface will cause the LM8333 to exit from
Halt mode. However, the LM8333 will not be able to ac-
knowledge the first bus cycle immediately following wake-up
from Halt mode. It will respond with a negative acknowledge-
ment, and the host should then repeat the cycle.
The LM8333 will be prevented from entering Halt mode if it
shares the bus with peripherals that are continuously active.
For lowest power consumption, the LM8333 should only
share the bus with peripherals that require little or no bus
activity after system initialization.
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7.0 Device Operation (Continued)
The data is sent from the slave to the host in the fourth byte.
This byte ends with a negative acknowledgement (NACK) to
indicate the end of the data.
FIGURE 9. Host Read Command
20210611
7.6 WAKE-UP FROM HALT MODE
Any bus transaction initiated by the host may encounter the
LM8333 device in Halt mode or busy with processing data,
such as controlling the FIFO buffer or executing interrupt
service routines.
Figure 10 shows the case in which the host sends a com-
mand while the LM8333 is in Halt mode (CPU clock is
stopped). Any activity on the ACCESS.bus wakes up the
LM8333, but it cannot acknowledge the first bus cycle im-
mediately after wake-up.
The host drives a Start condition followed by seven address
bits and a R/W bit. The host then releases SDA for one clock
period, so that it can be driven by the LM8333.
If the LM8333 does not drive SDA low during the high phase
of the clock period immediately after the R/W bit, the bus
cycle terminates without being acknowledged (shown as
NACK in Figure 10). The host then aborts the transaction by
sending a Stop condition. After aborting the bus cycle, the
host may then retry the bus cycle. On the second attempt,
the LM8333 will be able to acknowledge the slave address,
because it will be in Active mode.
Alternatively, the I2C specification allows sending a START
byte (00000001), which will not be acknowledged by any
device. This byte can be used to wake up the LM8333 from
Halt mode.
The LM8333 may also stall the bus transaction by pulling the
SCL low, which is a valid behavior defined by the I2C
specification.
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FIGURE 10. LM8333 Responds with NACK, Host Retries Command
20210612
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