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PDF AD8250 Data sheet ( Hoja de datos )
| Número de pieza | AD8250 | |
| Descripción | programmable instrumentation amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1. AD8250 datasheet pdf  Hay una vista previa y un enlace de descarga de AD8250 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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Data Sheet
10 MHz, 20 V/μs, G = 1, 2, 5, 10 iCMOS
Programmable Gain Instrumentation Amplifier
AD8250
FEATURES
Small package: 10-lead MSOP
Programmable gains: 1, 2, 5, 10
Digital or pin-programmable gain setting
Wide supply: ±5 V to ±15 V
Excellent dc performance
High CMRR 98 dB (minimum), G = 10
Low gain drift: 10 ppm/°C (maximum)
Low offset drift: 1.7 μV/°C (maximum), G = 10
Excellent ac performance
Fast settling time: 615 ns to 0.001% (maximum)
High slew rate: 20 V/µs (minimum)
Low distortion: −110 dB THD at 1 kHz
High CMRR over frequency: 80 dB to 50 kHz (minimum)
Low noise: 18 nV/√Hz, G = 10 (maximum)
Low power: 4.1 mA
APPLICATIONS
Data acquisition
Biomedical analysis
Test and measurement
GENERAL DESCRIPTION
The AD8250 is an instrumentation amplifier with digitally
programmable gains that has GΩ input impedance, low output
noise, and low distortion making it suitable for interfacing with
sensors and driving high sample rate analog-to-digital converters
(ADCs). It has a high bandwidth of 10 MHz, low THD of −110
dB and fast settling time of 615 ns (maximum) to 0.001%. Offset
drift and gain drift are guaranteed to 1.7 μV/°C and 10 ppm/°C,
respectively, for G = 10. In addition to its wide input common
voltage range, it boasts a high common-mode rejection of 80 dB
at G = 1 from dc to 50 kHz. The combination of precision dc
performance coupled with high speed capabilities makes the
AD8250 an excellent candidate for data acquisition. Furthermore,
this monolithic solution simplifies design and manufacturing
and boosts performance of instrumentation by maintaining a
tight match of internal resistors and amplifiers.
The AD8250 user interface consists of a parallel port that allows
users to set the gain in one of two ways (see Figure 1). A 2-bit word
sent via a bus can be latched using the WR input. An alternative is
to use the transparent gain mode where the state of the logic levels
at the gain port determines the gain.
FUNCTIONAL BLOCK DIAGRAM
–IN 1
DGND WR A1 A0
26
54
LOGIC
7 OUT
+IN 10
8
+VS
25
20
15
AD8250
3
–VS
Figure 1.
9
REF
G = 10
G=5
10
G=2
5
G=1
0
–5
–10
1k
10k 100k 1M
FREQUENCY (Hz)
Figure 2. Gain vs. Frequency
10M
100M
Table 1. Instrumentation Amplifiers by Category
General
Purpose
Mil
Zero Drift Grade
Low
Power
High Speed
PGA
AD82201
AD82311
AD620
AD6271
AD8250
AD8221
AD85531
AD621
AD6231
AD8251
AD8222
AD85551
AD524
AD82231
AD8253
AD82241
AD85561
AD526
AD8228
AD85571
AD624
1 Rail-to-rail output.
The AD8250 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making
it an excellent solution for applications where size and packing
density are important considerations.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Parameter
POWER SUPPLY
Operating Range
Quiescent Current, +IS
Quiescent Current, −IS
Over Temperature
TEMPERATURE RANGE
Specified Performance
Conditions
T = −40°C to +85°C
Min Typ
±5
4.1
3.7
−40
1 Add time for the output to slew and settle to calculate the total time for a gain change.
Max
±15
4.5
4.5
4.5
+85
TIMING DIAGRAM
WR
A0, A1
tWR-HIGH
tWR-LOW
tSU tHD
Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
AD8250
Unit
V
mA
mA
mA
°C
Rev. C | Page 5 of 24
5 Page 
Data Sheet
40
f = 1kHz
30
20
10
0
–10
–20
–30
–40
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity vs. Output Voltage, G = 2, RL = 10 kΩ, 2 kΩ, 600 Ω
40
f = 1kHz
30
20
10
0
–10
–20
–30
–40
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figure 25. Gain Nonlinearity vs. Output Voltage, G = 5, RL = 10 kΩ, 2 kΩ, 600 Ω
40
f = 1kHz
30
20
10
0
–10
–20
–30
–40
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figure 26. Gain Nonlinearity vs. Output Voltage, G = 10, RL = 10 kΩ, 2 kΩ, 600 Ω
AD8250
16
12
–13.8V, +6.9V
8
0V, +13.8V
VS = ±15V
+13.8V, +6.9V
4 0V, +3.7V
–3.8V, +1.9V
+3.9V, +1.9V
0 VS = ±5V
–3.8V, –1.9V
+3.8V, –2.1V
–4
0V, –4.0V
–8
–13.8V, –6.9V
–12
+13.8V, –6.9V
–16
–16
–12
0V, –14V
–8 –4
0
4
8
OUTPUT VOLTAGE (V)
12 16
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1
16
–14.1V, +13.6V
12
0V, +13.8V
VS = ±15V
+13.6V, +13.1V
8
+0V, +3.5V
4
–4.2V, +2.2V
+4.3V, +2.1V
0 VS = ±5V
–4.2V, –2.0V
–4
+4.3V, –2.1V
0V, –4.1V
–8
–12
–14.1V, –13.6V
–16
–16 –12 –8
0V, –14V
–4 0
4
OUTPUT VOLTAGE (V)
+13.6V, –13.1V
8 12 16
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 10
35
30 IB+
IB–
25 IOS
20
15
10
5
0
–5
–10
–15
–15
–10 –5 0 5 10
COMMON-MODE VOLTAGE (V)
15
Figure 29. Input Bias Current and Offset Current vs. Common-Mode Voltage
Rev. C | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD8250.PDF ] | |
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