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PDF AD5602 Data sheet ( Hoja de datos )
| Número de pieza | AD5602 | |
| Descripción | 8-/10-/12-Bit nanoDACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDACs with
I2C Compatible Interface in LFCSP and SC70
AD5602/AD5612/AD5622
FEATURES
Single 8-, 10-, 12-bit DACs, 2 LSB INL
6-lead LFCSP and SC70 packages
Micropower operation: 100 μA maximum at 5 V
Power down to <150 nA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
I2C compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
On-chip output buffer amplifier, rail-to-rail operation
Qualified for automotive applications
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
VDD GND
POWER-ON
RESET
AD5602/AD5612/AD5622
DAC
REGISTER
REF(+)
8-/10-/12-BIT
DAC
OUTPUT
BUFFER
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
ADDR SCL SDA
Figure 1.
Table 1. Related Devices
Device No.
AD5601/AD5611/AD5621
Description
2.7 V to 5.5 V, <100 μA, 8-, 10-, 12-bit
nanoDAC with SPI interface in tiny
LFCSP and SC70 packages
GENERAL DESCRIPTION
The AD5602/AD5612/AD5622, members of the nanoDAC®
family, are single 8-, 10-, 12-bit buffered voltage-out digital-to-
analog converters (DAC) that operate from a single 2.7 V to
5.5 V supply, consuming <100 μA at 5 V. These DACs come in
tiny LFCSP and SC70 packages. Each DAC contains an on-chip
precision output amplifier that allows rail-to-rail output swing
to be achieved.
The AD5602/AD5612/AD5622 use a 2-wire I2C compatible
serial interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.
The references for AD5602/AD5612/AD5622 derive from the
power supply inputs to give the widest dynamic output range. Each
device incorporates a power-on reset circuit that ensures the DAC
output powers up to 0 V and remains there until a valid write takes
place to the device. The devices contain a power-down feature
that reduces the current consumption of the devices to <150 nA
at 3 V and provides software selectable output loads while in
power-down mode. The devices are put into power-down mode
over the serial interface. The low power consumption of the
AD5602/AD5612/AD5622 in normal operation makes them
ideally suited for use in portable, battery operated equipment.
The typical power consumption is 0.4 mW at 5 V.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
PRODUCT HIGHLIGHTS
1. Available in 6-lead LFCSP and SC70 packages.
2. Maximum 100 μA power consumption, single-supply
operation. These devices operate from a single 2.7 V to 5.5 V
supply, typically consuming 0.2 mW at 3 V and 0.4 mW at
5 V, making them ideal for battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/μs.
4. Reference derived from the power supply.
5. Standard, fast, and high speed mode I2C interface.
6. Designed for very low power consumption.
7. Power-down capability. When powered down, the DAC
typically consumes <150 nA at 3 V.
8. Power-on reset and brownout detection.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5602/AD5612/AD5622
Parameter
t8
t9
t10
t11
t11A
t12
tSP4
Test Conditions/Comments2
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Fast mode
High speed mode
Limit at TMIN, TMAX
Min Max
4
0.6
160
1000
300
10 80
20 160
300
300
10 80
20 160
1000
300
10 40
20 80
1000
300
10 80
20 160
300
300
10 40
20 80
0 50
0 10
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
tFCL, fall time of SCL signal
Pulse width of spike suppressed
1 See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the
AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the device.
4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
TIMING DIAGRAM
SCL
SDA
t7
PS
t11
t2
t6
t4
t12
t1
t3
t6
t5
t10
S
Figure 2. 2-Wire Serial Interface Timing Diagram
t8
t9
P
Rev. D | Page 5 of 24
5 Page 
Data Sheet
0.10
0.09
0.08
0.07
0.06
VDD = 5V
0.05
0.04
VDD = 3V
0.03
0.02
0.01
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120 140
Figure 23. Supply Current vs. Temperature (3 V/5 V Supply)
70
VDD = 5V
60
TA = 25°C
50
VDD = 3V
40
30
20
10
0
0 2000 4000 6000 8000 10000 12000 14000 16000
DAC CODE
Figure 24. Supply Current vs. Digital Input Code
900
SCL/SDA INCREASING
800 VDD = 5V
700
600
500
SCL/SDA
400 INCREASING
VDD = 3V
300
SCL/SDA DECREASING
VDD = 5V
SCL/SDA DECREASING
VDD = 3V
200
100
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VLOGIC (V)
Figure 25. Supply Current vs. SCL/SDA Logic Voltage
AD5602/AD5612/AD5622
12 VDD = 3V
VIH = VDD
VIL = GND
10 TA = 25°C
8
6
4
2
0
VDD = 5V
VIH = VDD
VIL = GND
TA = 25°C
IDD (µA)
Figure 26. IDD Histogram (3 V/5 V Supply)
0.8
VDD = 5V
TA = 25°C
0.6
DAC LOADED WITH ZERO-SCALE CODE
0.4
0.2
0.0
–0.2
DAC LOADED WITH FULL-SCALE CODE
–0.4
–0.6
–15
–10 –5
0
5
I (mA)
10
Figure 27. Sink and Source Capability
15
VDD = 5V
TA = 25°C
VDD
CH1
VOUT = 70mV
CH2
CH1 = 1V/DIV, CH2 = 20mV/DIV, TIME BASE = 20µs/DIV
Figure 28. Power On Reset to 0 V
Rev. D | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5602.PDF ] | |
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