PDF DP83952 Data sheet ( Hoja de datos )

Número de pieza	DP83952
Descripción	Repeater Interface Controller with Security Features
Fabricantes	National Semiconductor
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No Preview Available ! www.DataSheet4U.com PRELIMINARY September 1995 DP83952 Repeater Interface Controller with Security Features (RICTM II) General Description The DP83952 RIC II Repeater Interface Controller is an ‘‘Enhanced’’ version of the DP83950 RIC RIC II is fully backward pin and functional compatible with the RIC The DP83952 RIC II has the same basic architecture as the RIC with additional feature enhancements RIC II provides addi- tional network security options additional statistics for re- peater activities and a faster processor interface When RIC II is used in a ‘‘non-secure’’ mode it functions in the same manner as the DP83950 RIC When RIC II is used in a ‘‘secure’’ mode it restricts unauthorized nodes from intrud- Y Separate Partition state machines for each port Y Compatible with 802 3k Hub Management requirements Y Provides port status information for LED displays in- cluding receive collision partition link status and jab- ber Y Power-up configuration options Repeater and Partition Specifications Transceiver Inter- face Status Display Processor Operations Y Simple processor interface for repeater management and port disable Y On-chip Event Counters and Event Flag Arrays ing and or eavesdropping into the network The RIC II uti- Y Serial Management Bus Interface to combine packet lizes internal CAMs to store compare addresses of valid and repeater status information nodes when network security is desired Y CMOS process for low power dissipation RIC II implements the IEEE 802 3 multiport repeater unit Y Single 5V supply specifications It is fully compliant with the 802 3 repeater specification for the repeater segment partition and jabber lockup protection state machines (Continued) Security Features Y Power-up configuration options Features Y Compliant with the IEEE 802 3 Repeater Specification Y 13 network connections (ports) per chip Y Prevents unauthorized eavesdropping and or intrusion on a per port basis Y 58 on-chip CAMs (Content Addressable Memory) allow storage of acceptable addresses Y Selectable on-chip twisted-pair transceivers Y Learn mode automatically records addresses of at- Y Cascadable for large hub applications Y Compatible with AUI compliant transceivers DataShteacehte4dUno.cdeosm Y On-chip Elasticity Buffer Manchester encoder and decoder 1 0 System Diagram DataShee TRI-STATE is a registered trademark of National Semiconductor Corporation RICTM Inter-RICTM and SONICTM are trademarks of National Semiconductor Corporation PAL is a registered trademark of and used under license from Advanced Micro Devices Inc GAL is a registered trademark of Lattice Semiconductor C1995 National Semiconductor Corporation TL F 12499 DataSheet4U.com DataSheet4 U .com TL F 12499 – 1 RRD-B30M115 Printed in U S A 1 page www.DataSheet4U.com et4U.com 2 0 Connection Diagrams (Continued) Pin Name TXO12Pb TXO12a TXO12b TXO12Pa RXI12b RXI12a VCC GND Pin No 40 39 38 37 36 35 34 33 RXI11b 32 RXI11a 31 TXO11Pa 30 TXO11b 29 TXO11a 28 TXO11Pb VCC GND TXO10Pb TXO10a TXO10b TXO10Pa RXI10b RXI10a VCC GND RXI9b 27 26 25 24 23 22 21 20 19 18 17 16 RXI9a 15 TXO9Pa 14 TXO9b 13 TXO9a 12 TXO9Pb 11 VCC GND TXO8Pb TXO8a TXO8b TXO8Pa RXI8b RXI8a VCC GND 10 9 8 7 6 5 4 3 2 1 Note NC e No Connect Pin Table (1 – 5 AUI a 6 – 13 T P Ports) Pin Name VCC GND IRC IRE IRD COLN VCC GND PKEN RXMPLL BUFEN RDY ELI RTI STR1 VCC GND STR0 ACTND ANYXND ACKO MRXC MEN MRXD MCRS VCC GND ACKI ACTNS ANYXNS PCOMP NC RXI13b RXI13a TXO13Pa TXO13b TXO13a TXO13Pb VCC GND Pin No Pin Name 80 VCC 79 GND 78 TX2b 77 TX2a 76 CD2b 75 CD2a 74 RX2a 73 RX2b 72 VCC 71 GND 70 RX1b 69 RX1a 68 CD1b 67 CD1a 66 TX1b 65 TX1a 64 VCC 63 GND 62 VCC 61 GND 60 CLKIN 59 PA4 D58ataSheetP4AU3 .com 57 PA2 56 PA1 55 PA0 54 VCCPLL 53 GNDPLL 52 MLOAD 51 CDEC 50 WR 49 RD 48 D7 47 D6 46 D5 45 D4 44 D3 43 D2 42 D1 41 D0 Pin No 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 Pin Name NC RXI7b RXI7a TXO7Pa TXO7b TXO7a TXO7Pb VCC GND TXO6Pb TXO6a TXO6b TXO6Pa RXI6b RXI6a VCC GND RX5a RX5b CD5a CD5b TX5a TX5b VCC GND TX4b TX4a CD4b CD4a RX4a RX4b VCC GND RX3a RX3b CD3a CD3b TX3a TX3b NC Pin No 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 5 DataSheet4U.com DataSheet4 U .com DataShee 5 Page www.DataSheet4U.com et4U.com 3 0 Pin Description Pin Name Driver Type IO Description NETWORK INTERFACE PINS (On-Chip Transceiver Mode) RXI2b to RXI13b TP I Twisted Pair Receive Input Negative RXI2a to RXI13a TP I Twisted Pair Receive Input Positive TXOP2b to TXOP13b TT O Twisted Pair Pre-Emphasis Transmit Output Negative TXO2b to TXO13b TT O Twisted Pair Transmit Output Negative TXO2a to TXO13a TT O Twisted Pair Transmit Output Positive TXOP2a to TXOP13a TT O Twisted Pair Pre-Emphasis Transmit Output Positive CD1a AL I AUI Collision Detect Input Positive CD1b AL I AUI Collision Detect Input Negative RX1a AL I AUI Receive Input Positive RX1b AL I AUI Receive Input Negative TX1a AD O AUI Transmit Output Positive TX1b AD O AUI Transmit Output Negative NETWORK INTERFACE PINS (External Transceiver Mode AUI Signal Level Compatibility Selected) TX2a to TX13a AL O Transmit Output Positive TX2b to TX13b AL O Transmit Output Negative CD2a to CD13a AL I Collision Input Positive CD2b to CD13b AL I Collision Input Negative RX2a to RX13a AL I Receive Input Positive RX2b to RX13b AL I Receive Input Negative CD1a CD1b AL I AUI Collision Detect Input Positive AL DaItaSheet4UAU.cI oComllision Detect Input Negative RX1a AL I AUI Receive Input Positive RX1b AL I AUI Receive Input Negative TX1a AD O AUI Transmit Output Positive TX1b AD O AUI Transmit Output Negative Note AD e AUI level and Drive compatible TP e Twisted Pair interface compatible AL e AUI Level compatible TT e TTL compatible I e Input O e Output B e Bi-directional Z e TRI-STATE C e CMOS compatible DataShee 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