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PDF DP83907 Data sheet ( Hoja de datos )
| Número de pieza | DP83907 | |
| Descripción | AT/LANTIC | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
November 1995
DP83907 AT LANTICTMII
General Description
The DP83907 Twisted-Pair Enhanced Coaxial Network In-
terface Controller is a CMOS VLSI device designed for easy
implementation of CSMA CD local area networks
Unique to the DP83907 is the integration of the entire bus
interface for PCAT ISA (Industry Standard Architecture) bus
based systems Hardware and software selectable options
allow the DP83907’s bus interface to be configured in the
same manner as an NE2000 Architecture All bus drivers
and control logic are integrated to reduce board cost and
area
Supported network interfaces include 10BASE5 or
10BASE2 Ethernet via an external transceiver connected to
its AUl port and Twisted-pair Ethernet (10BASE-T) using
the on-board transceiver The DP83907 provides the Ether-
net Media Access Control (MAC) Encode-Decode (ENDEC)
with an AUl interface and 10BASE-T transceiver functions
in accordance with the lEEE 802 3 standards
The DP83907’s integrated 10BASE-T transceiver fully com-
plies with the IEEE standard This functional block incorpo-
rates the receiver transmitter collision heartbeat loop-
back jabber and link integrity blocks as defined in the stan-
dard The transceiver when combined with equalization re-
sistors transmit receive filters and pulse transformers pro-
vides a complete physical interface from the DP83907’s
ENDEC module and the twisted pair medium (continued)
Features
Y Controller and integrated bus interface solution for IEEE
802 3 10BASE5 10BASE2 and 10BASE-T
Y Software compatible with industry standard Ethernet
Adapters Novell ’s NE2000
Y No external bus logic or drivers needed
Y Supports jumpered or jumperless configuration
Y Provides EEPROM interface for non-volatile storage of
configuration data user-defined data and Ethernet
Physical Address
Y Allows in-situ programming of EEPROM
Y Integrated controller ENDEC and transceiver
Y Full IEEE 802 3 compliant AUI interface
Y Single 5V supply
10BASE-T TRANSCEIVER MODULE
Y Integrates transceiver functionality
Y Transmitter and receiver functions
Y Collision detect heartbeat and jabber
Y Selectable link integrity test or link disable
Y Polarity Detection Correction
Y Auto switch
Y On chip filter
ENDEC MODULE
Y 10 Mbit s Manchester encoding decoding
Y Squelch on receive and collision pairs
MAC CONTROLLER MODULE
Y Software compatible with DP8390 DP83901 DP83902
Y Efficient buffer management implementation
IN-CIRCUIT TEST
1 0 System Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
AT LANTICTM is a trademark of National Semiconductor Corporation
Ethernet is a registered trademark of Xerox Corporation
NetWareTM is a trademark of Novell Incorporated
Novell is a registered trademark of Novell Incorporated
C1995 National Semiconductor Corporation TL F 12082
TL F 12082 – 1
RRD-B30M115 Printed in U S A
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2 0 Pin Description (Continued)
Pin No
Pin Name
Type
Description
NETWORK INTERFACE PINS
44 – 47 TxOda TXOb
TXOa TXOdb
O TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs are
TPI resistively combined external to the chip to produce a differential output signal with
equalization to compensate for Intersymbol Interference (ISI) on the twisted pair medium
42 43 RXIa RXIb
I TWISTED PAIR RECEIVE INPUTS These inputs feed a differential amplifier which passes
TPI valid data to the ENDEC module
33 34
TXb
TXa
O AUI TRANSMIT OUTPUT Differential driver which sends the encoded data to the
AUI transceiver
36 37
RXb
RXa
I AUI RECEIVE INPUT Differential receive input pair from the transceiver
AUI
38 39
CDb
CDa
I AUI COLLISION INPUT Differential collision pair input from the transceiver
AUI
55 ACT led
O ACTIVITY An open-drain active low output It is asserted for approximately 50 ms
LED whenever the DP83907 transmits or receives data in either AUI or TPI modes
56 COL led
O COLLISION An open-drain active low output It is asserted for approximately 50 ms
LED whenever the DP83907 detects a collision in either either AUI or TPI modes
54 GDLNK led
O GOOD LINK An open-drain active low output This pin operates as an output to display link
LED integrity status if this function has not been disabled by the GDLNK bit in Configuratioin
Register B
This output is off if the DP83907 is in AUI mode or if link testing is enabled and the link
integrity is bad (i e the twisted pair link has been broken)
This output is on if the DP83907 is in Twisted Pair interface (TPI) mode link integrity
checking is enabled and the link integrity is good (i e the twisted pair link has not been
broken) or if the link testing is disabled
53 REQ
I EQUALIZATION RESISTOR A resistor can be connected from this pin to GND or VCC to
change the equalization of the TP output
52 RTX
I TRANSMIT LEVEL RESISTOR A resistor can be connected from this pin to GND or VCC to
change the TP output amplitude level
59 X1 (OSCIN)
I CRYSTAL ON EXTERNAL OSCILLATOR INPUT
XTAL
58
X2 (OSCOUT)
O CRYSTAL FEEDBACK OUTPUT Used in crystal connections only Should be left
XTAL unconnected when using an oscillator module
31 THIN
O THIN CABLE This output is high if DP83907 is configured for thin cable It can be used to
DCDC enable the DC-DC converter required by the thin Ethernet configuration
Note Driver Types are I e Input O e Output I O e Bi-directional Output OCH e Open Collector 3ST e TRI-STATE Output TTL e TTL Compatible
AUI e Attachment Unit Interface TPI e Twisted Pair Interface LED e LED Drive MOS e CMOS Level Compatible XTAL e Crystal
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4 0 Functional Description (Continued)
On a remote read the DP83907 moves data from its internal
memory map to the I O port and the host system reads it by
using an ‘‘INW’’ or ‘‘INSW’’ instruction from the I O address
of the data transfer port If the system attempts to read the
port before DP83907 has written the next word of data to it
DP83907 will insert wait states into the system cycle using
the CHRDY line DP83907 will not begin the next memory
read until the previous word of data has been read
On a remote write the system writes data to the I O port
using an ‘‘OUTW’’ or ‘‘OUTSW’’ instruction and DP83907
moves it to its buffer memory If the system attempts to
write to the port before DP83907 has moved the data to
memory DP83907 will insert wait states into the system cy-
cle using the CHRDY line DP83907 will not begin the next
memory write until a new word has been written to the I O
port
Addresses 00H to 1FH are specified as the PROM space
for compatibility with the NE2000 Architecture This is actu-
ally an array of 8-bit registers which are loaded from an
external EEPROM after DP83907 is initialized by an ISA RE-
SET They should contain the same data as the PROM did
in the NE2000 Architecture and in the same format To
transfer the data out the user must initiate a 16-bit DMA
read transfer and discard the most significant byte of data
on each transfer
At address 00H of the PROM is a six byte Ethernet address
for this node The upper two addresses of the PROM store
contain bytes which identify whether the DP83907 is in 8-bit
or 16-bit mode For 16-bit mode these bytes both contain
the value 57H for 8-bit mode they both contain 42H
8-BIT I O PORT COMPATIBLE MODE
This mode is compatible with the 8-bit mode offered by No-
vells NE2000 Architecture The NE2000 automatically de-
tects whether it is in an 8-bit or 16-bit slot and configures
itself appropriately As explained in the previous para-
graphs the user can determine whether the board is in 8-bit
or 16-bit mode by reading the PROM In 8-bit mode only
8 Kbytes of RAM are addressable as in the 8-bit mode of
the NE2000 Architecture The I O map is the same as the
16-bit mode the memory map is shown in Figure 5 Again
the PROM has only a partial decode so is mirrored at all
addresses up to 4000H The PROM still occupies 32 bytes
of address space although it only has 16 bytes of data as
the data at all odd address locations is merely a mirror of
the data at the previous even address location
A low cost card using only one 8 Kbyte RAM can be de-
signed If the function on MSA9 is left unconnected then
the DP83907 will always operate in 8-bit mode regardless
of the slot the board is in
0000h
0020h
PROM
4000h
6000h
Aliased PROM
8k x 8 BUFFER RAM
RESERVED
7FFFh
(a)
D15 D0
1Eh 42h
42h
1Ch 42h
42h
RESERVED
RESERVED
0Ah E’net Address 5 E’net Address 5
08h E’net Address 4 E’net Address 4
06h E’net Address 3 E’net Address 3
04h E’net Address 2 E’net Address 2
02h E’net Address 1 E’net Address 1
00h E’net Address 0 E’net Address 0
(b)
FIGURE 5 a) 8-Bit NIC Core’s Memory Map
b) 8-Bit PROM Map
4 2 POWER ON RESET OPERATION
The DP83907 configures itself after a Reset signal is ap-
plied To be recognized as a valid Power-On-Reset the Re-
set signal must be active for at least 415 ms Figure 6 shows
how the RESET circuitry operates
TL F 12082 – 6
FIGURE 6 RESET Operation
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DP83907.PDF ] | |
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