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What is DP83902A?

This electronic component, produced by the manufacturer "National Semiconductor", performs the same function as "ST-NICTM Serial Network Interface Controller for Twisted Pair".


DP83902A Datasheet PDF - National Semiconductor

Part Number DP83902A
Description ST-NICTM Serial Network Interface Controller for Twisted Pair
Manufacturers National Semiconductor 
Logo National Semiconductor Logo 


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PRELIMINARY
November 1995
DP83902A ST-NICTM
Serial Network Interface Controller for Twisted Pair
General Description
The DP83902A Serial Network Interface Controller for
Twisted Pair (ST-NIC) is a microCMOS VLSI device de-
signed for easy implementation of CSMA CD local area net-
works These include Ethernet (10BASE5) Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T) The
overall ST-NIC solution provides the Media Access Control
(MAC) and Encode-Decode (ENDEC) with an AUI interface
and 10BASE-T transceiver functions in accordance with the
IEEE 802 3 standards
The DP83902A’s 10BASE-T transceiver fully complies with
the IEEE standard This functional block incorporates the
receiver transmitter collision heartbeat loopback jabber
and link integrity blocks as defined in the standard The
transceiver when combined with equalization resistors
transmit receive filters and pulse transformers provides a
complete physical interface from the DP83902A’s ENDEC
module and the twisted pair medium
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock loop decoder at 10 Mbit sec Also included are colli-
sion detect translator and diagnostic loopback capability
The ENDEC module interfaces directly to the transceiver
module and also provides a fully IEEE compliant AUI (At-
tachment Unit Interface) for connection to other media
transceivers
(Continued)
Features
Y Single chip solution for IEEE 802 3 10BASE-T
Y Integrated controller ENDEC and transceiver
Y Full AUI interface
Y No external precision components required
Y 3 levels of loopback supported
Transceiver Module
Y Integrates transceiver electronics including
Transmitter and receiver
Collision detect heartbeat and jabber timer
Link integrity test
Y Link disable and polarity detection correction
Y Integrated smart receive squelch
Y Reduced squelch level for extended distance cable op-
eration (100-pin QFP version)
ENDEC Module
Y 10 Mb s Manchester encoding decoding plus clock re-
covery
Y Transmitter half or full step mode
Y Squelch on receive and collision pairs
Y Lock time 5 bits typical
Y Decodes Manchester data with up to g18 ns jitter
MAC Controller Module
Y 100% DP8390 software hardware compatible
Y Dual 16-bit DMA channels
Y 16-byte internal FIFO
Y Efficient buffer management implementation
Y Independent system and network clocks
Y Supports physical multicast and broadcast address fil-
tering
Y Network statistics storage
1 0 System Diagram
Station or DTE
TRI-STATE is a registered trademark of National Semiconductor Corporation
ST-NICTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11157
TL F 11157 – 1
RRD-B30M115 Printed in U S A
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DP83902A equivalent
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2 0 Pin Description (Continued)
PQFP
Pin No
PLCC AVJG
Pin No Pin No
Pin
Name
BUS INTERFACE PINS (Continued)
4–8
10 – 12
14 15 17
18 22 23
25 26
12 – 23
28 – 31
2–4 6
7 9–15
20 – 23
AD0 –
AD15
27 32 25 ADS0
28 33 26 CS
29 34 27 MWR
30 35 28 MRD
31 36 29 SWR
32 37 30 SRD
33 38 31 ACK
36 40 34 BSCK
37 41 35 RACK
39 42 36 PWR
41 43 37 READY
42 44 39 PRQ
ADS1
IO
IOZ
IOZ
I
OZ
OZ
I
I
O
I
I
O
I
OZ
Description
MULTIPLEXED ADDRESS DATA BUS
 Register Access with DMA inactive CS low and ACK returned from
DP83902A pins AD0–AD7 are used to read and write register data AD8–
AD15 float during I O transfers SRD SWR pins are used to select
direction of transfer
 Bus Master with BACK input asserted
During t1 of memory cycle AD0 – AD15 contain address
During t2 t3 t4 AD0 – AD15 contain data (word transfer mode)
During t2 t3 t4 AD0–AD7 contain data AD8–AD15 contain address (byte
transfer mode)
Direction of transfer is indicated by DP83902A on MWR MRD lines
ADDRESS STROBE 0
 Input with DMA inactive and CS low latches RA0–RA3 inputs on falling
edge If high data present on RA0–RA3 will flow through latch
 Output When Bus Master latches address bits (AD0–AD15) to external
memory during DMA transfers
CHIP SELECT Chip Select places controller in slave mode for mP access to
internal registers Must be valid through data portion of bus cycle RA0 – RA3
are used to select the internal register SWR and SRD select direction of
data transfer
MASTER WRITE STROBE (Strobe for DMA transfers)
Active low during write cycles (t2 t3 tw) to buffer memory Rising edge
coincides with the presence of valid output data TRI-STATE until BACK
asserted
MASTER READ STROBE (Strobe for DMA transfers)
Active during read cycles (t2 t3 tw) to buffer memory Input data must be
valid on rising edge of MRD TRI-STATE until BACK asserted
SLAVE WRITE STROBE Strobe from CPU to write an internal register
selected by RA0 – RA3 Data is latched into the DP83902A on the rising
edge of this input
SLAVE READ STROBE Strobe from CPU to read an internal register
selected by RA0 – RA3 The register data is output when SRD goes low
ACKNOWLEDGE Active low when DP83902A grants access to CPU Used
to insert WAIT states to CPU until DP83902A is synchronized for a register
read or write operation
BUS CLOCK This clock is used to establish the period of the DMA memory
cycle Four clock cycles (t1 t2 t3 t4) are used per DMA cycle DMA
transfers can be extended by one BSCK increment using the READY input
READ ACKNOWLEDGE Indicates that the system DMA or host CPU has
read the data placed in the external latch by the DP83902A The DP83902A
will begin a read cycle to update the latch
PORT WRITE Strobe used to latch data from the DP83902A into external
latch for transfer to host memory during Remote Read transfers The rising
edge of PWR coincides with the presence of valid data on the local bus
READY This pin is set high to insert wait states during a DMA transfer The
DP83902A will sample this signal at t3 during DMA transfers
PORT REQUEST ADDRESS STROBE 1
 32-BIT MODE If LAS is set in the Data Configuration Register this line is
programmed as ADS1 It is used to strobe addresses A16 – A31 into
external latches (A16 – A31 are the fixed addresses stored in RSAR0
RSAR1) ADS1 will remain at TRI-STATE until BACK is received
 16-BIT MODE If LAS is not set in the Data Configuration Register this
line is programmed as PRQ and is used for Remote DMA Transfers The
DP83902A initiates a single remote DMA read or write operation by
asserting this pin In this mode PRQ will be a standard logic output
Note This line will power up as TRI-STATE until the Data Configuration Register is programmed
5
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Featured Datasheets

Part NumberDescriptionMFRS
DP83902AThe function is ST-NICTM Serial Network Interface Controller for Twisted Pair. National SemiconductorNational Semiconductor
DP83902AThe function is DP83902A ST-NIC Serial Network Interface Controller for Twisted Pair (Rev. A). Texas InstrumentsTexas Instruments

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