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Número de pieza | TC74LVX138FN | |
Descripción | 3-TO-8 LINE DECODER | |
Fabricantes | Toshiba Semiconductor | |
Logotipo | ||
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TC74LVX138F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74LVX138F,TC74LVX138FN,TC74LVX138FT
3-to-8 Line Decoder
The TC74LVX138F/ FN/ FT is a high-speed CMOS 3-to-8 line
decoder fabricated with silicon gate CMOS technology. Designed
for use in 3-V systems, it achieves high-speed operation while
maintaining the CMOS low power dissipation.
This device is suitable for low-voltage and battery operated
systems.
When the device is enabled, 3 Binary Select inputs (A, B and C)
determine which one of the outputs (Y0-Y7) will go low. When
enable input G1 is held low or either G2A or G2B is held high,
decoding function is inhibited and all outputs go high.
G1, G2A, and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
An input protection circuit ensures that 0 to 5.5V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5V to 3V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74LVX138F
TC74LVX138FN
Features
www.DataSheet4U.com· High-speed: tpd = 5.5 ns (typ.) (VCC = 3.3 V)
TC74LVX138FT
· Low power dissipation: ICC = 4 µA (max) (Ta = 25°C)
· Input voltage level: VIL = 0.8 V (max) (VCC = 3 V)
VIH = 2.0 V (min) (VCC = 3 V)
· Power-down protection provided on all inputs
· Balanced propagation delays: tpLH ≈ tpHL
· Pin and function compatible with 74HC138
Weight
SOP16-P-300-1.27: 0.18 g (typ.)
SOL16-P-150-1.27: 0.12 g (typ.)
TSSOP16-P-0044-0.65: 0.06 g (typ.)
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1 2001-11-12
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TC74LVX138F/FN/FT
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay time
(A, B, C- Y )
Symbol Test Condition
VCC (V) CL (pF)
tpLH
tpHL
15
2.7
50
¾
15
3.3 ± 0.3
50
Propagation delay time
(G1- Y )
tpLH
tpHL
15
2.7
50
¾
15
3.3 ± 0.3
50
Propagation delay time
( G2 - Y )
tpLH
tpHL
15
2.7
50
¾
15
3.3 ± 0.3
50
Output to output skew
tosLH
tosHL
2.7
(Note 1)
3.3 ± 0.3
50
50
Input capacitance
Power dissipation capacitance
CIN
CPD
(Note 2)
(Note 3)
Ta = 25°C
Min Typ. Max
¾ 7.1 13.8
¾ 9.6 17.3
¾ 5.5 8.8
¾ 8.0 12.3
¾ 8.7 16.3
¾ 11.2 19.8
¾ 6.8 10.6
¾ 9.3 14.1
¾ 8.8 16.0
¾ 11.3 19.5
¾ 6.9 10.4
¾ 9.4 13.9
¾ ¾ 2.5
¾ ¾ 2.5
¾ 4 10
¾ 34 ¾
Ta = -40 to
85°C
Min Max
1.0 16.5
1.0 20.0
1.0 10.5
1.0 14.0
1.0 19.5
1.0 23.0
1.0 12.5
1.0 16.0
1.0 18.5
1.0 22.0
1.0 11.5
1.0 15.0
¾ 2.5
¾ 2.5
¾ 10
¾¾
Unit
ns
ns
ns
ns
pF
pF
Note 1: Parameter guaranteed by design.
(tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn|)
www.DataSheet4U.comNote 2: Parameter guaranteed by design.
Note 3:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption.
Average operating current can be obtained by the equation:
ICC (opr) = CPD・VCC・fIN + ICC
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5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet TC74LVX138FN.PDF ] |
Número de pieza | Descripción | Fabricantes |
TC74LVX138F | 3-TO-8 LINE DECODER | Toshiba Semiconductor |
TC74LVX138FN | 3-TO-8 LINE DECODER | Toshiba Semiconductor |
TC74LVX138FT | 3-TO-8 LINE DECODER | Toshiba Semiconductor |
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