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PDF CY7C68300B Data sheet ( Hoja de datos )
| Número de pieza | CY7C68300B | |
| Descripción | (CY7C68300B / CY7C68301B / CY7C68320 / CY7C68321) EZ-USB AT2LPTM USB 2.0 to ATA/ATAPI Bridge | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C68300B/CY7C68301B
CY7C68320/CY7C68321
EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
1.0 Features (CY7C68300B/CY7C68301B and
CY7C68320/CY7C68321)
• Fixed-function mass storage device—requires no firmware
code
• Two power modes: Self-powered and USB bus-powered to
enable bus powered CF readers and truly portable USB
hard drives
• Certified compliant for USB 2.0 (TID# 40460273), the USB
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification
• Operates at high (480-Mbps) or full (12-Mbps) speed USB
• Complies with ATA/ATAPI-6 specification
• Supports 48-bit addressing for large hard drives
• Supports ATA security features
• Supports all ATA commands via ATACB function
• Supports mode page 5 for BIOS boot support
• Supports ATAPI serial number VPD page retrieval for Digital
Rights Management (DRM) compatibility
• Supports PIO modes 0, 3, 4, multiword DMA mode 2, and
UDMA modes 2, 3, 4
• Uses one external serial EEPROM for storage of USB
descriptors and device configuration data
• ATA interface IRQ signal support
• Support for one or two ATA/ATAPI devices
2.0 Block Diagram
• Support for CompactFlash and one ATA/ATAPI device
• Can place the ATA interface in high-impedance (Hi-Z) to
allow sharing of the ATA bus with another controller (e.g.,
an IEEE-1394 to ATA bridge chip or MP3 Decoder)
• Support for board-level manufacturing test via USB
interface
• Low-power 3.3V operation
• Fully compatible with native USB mass storage class drivers
• Cypress mass storage class drivers available for Windows
(98SE, ME, 2000, XP) and Mac OS X
1.1 Features (CY7C68320/CY7C68321 only)
• Supports HID interface or custom GPIOs to enable features
such as single button backup, power-off, LED-based notifi-
cation, etc.
• Lead-free 56-pin QFN and 100-pin TQFP packages
• CY7C68321 is ideal for battery-powered designs
• CY7C68320 is ideal for self- and bus-powered designs
1.2 Features (CY7C68300B/CY7C68301B only)
• Pin-compatible with CY7C68300A (using Backward
Compatibility mode)
• Lead-free 56-pin SSOP and 56-pin QFN packages
• CY7C68301B is ideal for battery-powered designs
• CY7C68300B is ideal for self- and bus-powered designs
SCL
I2C Bus Controller
SDA
24
MHz
XTAL
VBUS
D+
D-
PLL
USB 2.0 XCVR
Misc control signals
Internal Control Logic
ATA_EN (ATA Interface 3-state)
ATA Interface
Control Signals
Control
ATA
Interface
Logic
16 Bit ATA Data
CY Smart USB
FS/HS Engine
4kByte FIFO
Data
Cypress Semiconductor Corporation
Document 38-08033 Rev. *D
Figure 2-1. Block Diagram
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised February 21, 2005
1 page  
www.DataSheet4U.com
CY7C68300B/CY7C68301B
CY7C68320/CY7C68321
IORDY 1
DMARQ 2
AVCC 3
XTALOUT 4
XTALIN 5
AGND 6
VCC 7
DPLUS 8
DMINUS 9
GND 10
VCC 11
GND 12
GPIO1 13
GND 14
EZ-USB AT2LP
CY7C68320
CY7C68321
56-pin QFN
42 RESET#
41 GND
40 ARESET#
39 DA2
38 CS1#
37 CS0#
36 GPIO0
35 DA1
34 DA0
33 INTRQ
32 VCC
31 DMACK#
30 DIOR#
29 DIOW#
Figure 5-4. 56-pin QFN Pinout (CY7C68320/CY7C68321)
Document 38-08033 Rev. *D
Page 5 of 36
5 Page 
www.DataSheet4U.com
CY7C68300B/CY7C68301B
CY7C68320/CY7C68321
No No
USB Interrupt
Pipe Polled?
Yes
Int_Data = 1?
No
NAK Request
Yes
Return Interrupt Data
Set Int_Data = 0
SYSIRQ=1?
Yes
Yes
Latch State of IO Pins
Set Int_Data = 1
Int_Data = 0
and
SYSIRQ=0?
No
Figure 5-7. SYSIRQ Latching Algorithm
5.3.5 DRVPWRVLD
When this pin is enabled via EEPROM byte 8, bit 0, the AT2LP
will inform the host that a removable device, such as a CF
card, is present. The CY7C68300B/CY7C68301B will use
DRVPWRVLD to detect that the removable device is present.
Pin polarity is controlled by bit 1 of EEPROM address 8. When
DRVPWRVLD is deasserted, the AT2LP will report a “no
media present” status (ASC = 0x3A, ASQ = 0x00) to the host.
When the media has been detected again, the AT2LP will
report a “media changed” status to the host (ASC = 0x28,
ASQ = 0x00).
When a removable device is used, it is always the master
device. Only one removable device may be attached to the
AT2LP. If the system only contains a removable device,
EEPROM byte 8, bit 6 must be set to ‘0’ to disable ATA device
detection at start-up. If a non-removable device is connected
in addition to a removable media device, it must be configured
as a slave (device address 1).
DRVPWRVLD can also be configured as an input. See
Section 6.0 HID Functions for Button Controls.
5.3.6 GPIO Pins
The GPIO pins allow for a general purpose Input/Output
interface. There are several different interfaces to the GPIO
pins:
• Configuration bytes 0x09 and 0x0A contain the default set-
tings for the GPIO pins.
• The host can modify the settings of the GPIO pins during
operation. This is done with vendor-specific commands de-
scribed in Section 8.6.
• The status of the GPIO pins is also returned on the interrupt
endpoint (EP1) in response to a SYSIRQ. See section 5.3.3
for SYSIRQ details.
GPIO2_nHS also has an alternate function. If the “HS Indicator
Enable” configuration (bit 2 of EEPROM address 8) is set, the
GPIO2_nHS pin will reflect the operating speed of the device
(full- or high-speed USB).
5.3.7 LOWPWR#
LOWPWR# is an output pin that is driven to ‘0’ when the
AT2LP is active. LOWPWR# is placed in Hi-Z when the AT2LP
is in a suspend state.
5.3.8 ATA Interface Pins
Design practices for signal integrity as outlined in the
ATA/ATAPI-6 Specification should be followed with systems
that utilize a ribbon cable interconnect between the
CY7C68300B/CY7C68301B’s ATA interface and the attached
ATA/ATAPI device, especially if Ultra DMA Mode is utilized.
5.3.9 VBUS_ATA_ENABLE
VBUS_ATA_ENABLE is typically used to indicate to the
AT2LP that power is present on VBUS. This pin is polled by
the AT2LP at start-up and then every 20ms thereafter. If this
pin is ‘1’, the internal 1.5K pull-up is attached to D+. If this pin
is ‘0’, the AT2LP will release the pull-up on D+ as required by
the USB specification. Also, If EEPROM byte 8, bit 4 is ‘0’, the
ATA interface pins will be placed in a high impedance (Hi-Z)
state when VBUS_ATA_ENABLE is ‘0’. If EEPROM byte 8, bit
4 is ‘1’, the ATA interface pins will still be driven when
VBUS_ATA_ENABLE is ‘0’.
Document 38-08033 Rev. *D
Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C68300B.PDF ] | |
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