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A1020B Datasheet PDF - Actel

Part Number A1020B
Description FPGAs
Manufacturers Actel 
Logo Actel Logo 

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A1020B datasheet, circuit
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v3.0
RadTolerant FPGAs
Features
General Characteristics
• Tested Total Ionizing Dose (TID) Survivability Level
• No Single Event Latch-up Below a Minimum LET
Threshold of 80 MeV-cm2/mg for All RT Devices
• Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and 256-Pin
Ceramic Quad Flat Pack
• Offered as Class B and E-Flow (Actel Space Level Flow)
• QML Certified Devices
• 100% Military Temperature Tested (–55°C to +125°C)
High Density and Performance
• 4,000 to 20,000 Logic Equivalent Gates
• 2,000 to 10,000 ASIC Equivalent Gates
• Up to 85 MHz Internal Performance
• Up to 60 MHz System Performance
• Up to 228 User I/Os
• Up to Four Fast, Low-Skew Clock Networks
Easy Logic Integration
• Non-Volatile, User Programmable
• Pin-Compatible Commercial Devices Available for
Prototyping
• Highly Predictable Performance with 100% Automatic
Place and Route
• 100% Resource Utilization with 100% Pin-Locking
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• Permanently Programmed for Operation on Power-Up
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer
General Description
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 failures-in-time (FITs), corresponding
to a useful life of more than 40 years. Actel FPGAs are
production-proven, with more than five million devices
shipped and more than one trillion antifuses manufactured.
Actel devices are fully tested prior to shipment, with an
out-going defect level of only 122 ppm (further reliability data
is available in the Actel Device Reliability Report at
http://www.actel.com/hirel).
Additionally, the programmable architecture of these devices
offers high performance, design flexibility, and fast and
inexpensive prototyping—all without the expense of test
vectors, NRE charges, long lead times, and schedule and cost
penalties for design refinements.
Product Family Profile
Device
Capacity
System Gates
Logic Gates
ASIC Equivalent Gates
PLD Equivalent Gates
mTTL Equivalent Package
o20-Pin PAL Equivalent Packages
.cLogic Modules
US-Modules
t4C-Modules
eUser I/Os (Maximum)
hePerformance
SSystem Speed (Maximum)
taPackages (by Pin Count)
a CQFP
w.D January 2000
ww © 2000 Actel Corporation
RT1020
6,000
4,000
2,000
5,000
50
20
547
N/A
547
69
20 MHz
84
RT1280A
24,000
16,000
8.000
20,000
200
80
1,232
624
608
140
40 MHz
172
RT1425A
7,500
5,000
2,500
6,250
60
25
310
160
150
100
60 MHz
132
RT1460A
18,000
12,000
6,000
15.000
150
60
848
432
416
168
60 MHz
196
RT14100A
30,000
20,000
10,000
25,000
250
100
1,377
697
680
228
60 MHz
256
1

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A1020B equivalent
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RadTolerant FPGAs
RadTolerant Architecture
The Actel architecture is composed of fine-grained logic
modules that produce fast, efficient logic designs. All devices
are composed of logic modules, routing resources, clock
networks, and I/O modules which are the building blocks for
fast logic designs.
Logic Modules
These RadTolerant devices contain two types of logic
modules, combinatorial (C-modules) and sequential
(S-modules). RT1020 and A1020B devices contain only
C-modules.
The C-module, shown in Figure 1, implements the following
function:
Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
where:
S0=A0*B0
S1=A1+B1
The S-module, shown in Figure 2, is designed to implement
high-speed sequential functions within a single logic module.
The S-module implements the same combinatorial logic
function as the C-module while adding a sequential element.
The sequential element can be configured as either a D-type
A0
B0
A1
B1
S0
D00
D00
D10
D11
S1
Y
Figure 1 • C-Module Implementation
flip-flop or a transparent latch. To increase flexibility, the
S-module register can be by-passed so it implements purely
combinatorial logic.
Flip-flops can also be created using two C-modules. The SEU
characteristics differ between an S-module flip-flop and a
flip-flop created using two C-modules. For details see the
Design Techniques for RadHard Field Programmable Gate
Arrays application note at http://www.actel.com/hirel.
D00
D01
YD
Q OUT
D10
D11 S0
S1
CLR
D00
D01
YD
Q OUT
D10
D11 S0 GATE
S1
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D0
mD1
.coS
Y
DQ
GATE
CLR
OUT
heet4UUp to 4-Input Function Plus Latch with Clear
www.DataSFigure 2 • S-Module Implementation
Up to 7-Input Function Plus Latch
D00
D01 Y OUT
D10
D11 S0
S1
Up to 8-Input Function (Same as C-Module)
5

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Information Total 30 Pages
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