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A1020B PDF Datasheet - Actel

Part Number A1020B
Description FPGAs
Manufacturers Actel 
Logo Actel Logo 
Preview
Preview ( 30 pages )
		
A1020B datasheet, circuit
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v3.0
RadTolerant FPGAs
Features
General Characteristics
• Tested Total Ionizing Dose (TID) Survivability Level
• No Single Event Latch-up Below a Minimum LET
Threshold of 80 MeV-cm2/mg for All RT Devices
• Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and 256-Pin
Ceramic Quad Flat Pack
• Offered as Class B and E-Flow (Actel Space Level Flow)
• QML Certified Devices
• 100% Military Temperature Tested (–55°C to +125°C)
High Density and Performance
• 4,000 to 20,000 Logic Equivalent Gates
• 2,000 to 10,000 ASIC Equivalent Gates
• Up to 85 MHz Internal Performance
• Up to 60 MHz System Performance
• Up to 228 User I/Os
• Up to Four Fast, Low-Skew Clock Networks
Easy Logic Integration
• Non-Volatile, User Programmable
• Pin-Compatible Commercial Devices Available for
Prototyping
• Highly Predictable Performance with 100% Automatic
Place and Route
• 100% Resource Utilization with 100% Pin-Locking
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• Permanently Programmed for Operation on Power-Up
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer
General Description
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 failures-in-time (FITs), corresponding
to a useful life of more than 40 years. Actel FPGAs are
production-proven, with more than five million devices
shipped and more than one trillion antifuses manufactured.
Actel devices are fully tested prior to shipment, with an
out-going defect level of only 122 ppm (further reliability data
is available in the Actel Device Reliability Report at
http://www.actel.com/hirel).
Additionally, the programmable architecture of these devices
offers high performance, design flexibility, and fast and
inexpensive prototyping—all without the expense of test
vectors, NRE charges, long lead times, and schedule and cost
penalties for design refinements.
Product Family Profile
Device
Capacity
System Gates
Logic Gates
ASIC Equivalent Gates
PLD Equivalent Gates
mTTL Equivalent Package
o20-Pin PAL Equivalent Packages
.cLogic Modules
US-Modules
t4C-Modules
eUser I/Os (Maximum)
hePerformance
SSystem Speed (Maximum)
taPackages (by Pin Count)
a CQFP
w.D January 2000
ww © 2000 Actel Corporation
RT1020
6,000
4,000
2,000
5,000
50
20
547
N/A
547
69
20 MHz
84
RT1280A
24,000
16,000
8.000
20,000
200
80
1,232
624
608
140
40 MHz
172
RT1425A
7,500
5,000
2,500
6,250
60
25
310
160
150
100
60 MHz
132
RT1460A
18,000
12,000
6,000
15.000
150
60
848
432
416
168
60 MHz
196
RT14100A
30,000
20,000
10,000
25,000
250
100
1,377
697
680
228
60 MHz
256
1

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A1020B pdf, schematic
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Device Description
The RT1020 device contains the same architecture as the
A1020, A1020A, and A1020B devices. The architecture, a
combinatorial logic module, is a logic structure that has 8
inputs and 1 output. The logic itself is comprised of a 4-input
MUX, as described in Figure 3 on page 6. In addition, since
the RT1020 device contains the same number of gates and
I/Os and has the same operating voltage as its commercial
equivalent (A1020B), an inexpensive commercial grade
A1020B-CQ84 device can be used during the prototype phase,
and replaced by the RT1020 in the flight units.
The RT1280A device uses the A1280A die from the ACT 2
family of FPGAs. It utilizes a two-module architecture,
consisting of combinatorial modules (C-modules) and
sequential modules (S-modules) optimized for both
combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the RT1280A has
8,000 ASIC-equivalent gates and 140 user I/Os.
The RT1280A device is fully pin- and function-compatible
with the commercially-equivalent A1280A-CQ172C device for
easy and inexpensive prototyping.
The RT1425A, RT1460A and RT14100A devices use the
A1425A, A1460A and A14100A die, respectively. These devices
are derived from the ACT 3 family of FPGAs, which also utilize
the two-module channeled array architecture, and offer faster
performance than the RT1280A.
These devices also have fully pin- and function-compatible
commercially-equivalent devices for easy and inexpensive
prototyping. The A1425A-CQ132C is used for the RT1425A, the
A1460A-CQ196C is used for the RT1460A, and the
A14100A-CQ256C is used for the RT14100A.
Radiation Survivability
Total dose results are summarized in two ways. First by the
maximum total dose level that is reached when the parts fail
to meet a device specification but remain functional. For
Actel FPGAs, the parameter that exceeds the specification
first is ICC, the standby supply current. Second by the
maximum total dose that is reached prior to the functional
failure of the device.
The RT devices have varying total dose radiation survivability.
The ability of these devices to survive radiation effects is both
omdevice and lot dependent. The customer must evaluate and
.cdetermine the applicability of these devices to their specific
design and environmental requirements.
t4UTypical results for the RT1020 device has shown ~100Krads
e(Si) for standby ICC and >100Krads for functional failure.
eRT1280A device have shown results from 4 to 10Krads (Si) for
hstandby ICC, and 7 to 18Krads for functional failure. ACT 3
taSdevices typical results have shown 10 to 28Krads for ICC, and
20 to 77Krads for functional failure.
www.Da2
Actel will provide total dose radiation testing along with the
test data on each pedigreed lot that is available for sale.
These reports are available on our website or you can contact
your local sales representative to receive a copy. A listing of
available lots and devices is also provided. These results are
only provided for reference and for customer information.
For a radiation performance summary, see Radiation
Performance of Actel Products on the Actel Website at
http://www.actel.com/hirel.
This summary will also show single event upset (SEU) and
single event latch up (SEL) testing that has been performed
on Actel FPGAs.
QML Certification
Actel has achieved full QML certification, demonstrating that
quality management, procedures, processes, and controls are
in place and comply with MIL-PRF-38535, the performance
specification used by the Department of Defense for
monolithic integrated circuits. QML certification is a good
example of Actel's commitment to supplying the highest
quality products for all types of high-reliability, military and
space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows for
a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
Disclaimer
All radiation performance information is provided for
information purposes only and is not guaranteed. The total
dose effects are lot-dependent, and Actel does not guarantee
that future devices will continue to exhibit similar radiation
characteristics. In addition, actual performance can vary
widely due to a variety of factors, including but not limited to,
characteristics of the orbit, radiation environment, proximity
to satellite exterior, amount of inherent shielding from other
sources within the satellite, and actual bare die variations.
For these reasons, Actel does not guarantee any level of
radiation survivability, and it is solely the responsibility of the
customer to determine whether the device will meet the
requirements of the specific design.
Development Tool Support
The RadTolerant devices are fully supported by Actel’s line of
FPGA development tools, including the Actel DeskTOP series
and Designer Advantage tools. The Actel DeskTOP Series is
an integrated design environment for PCs that includes
design entry, simulation, synthesis, and place and route tools.
Designer Advantage is Actel’s suite of FPGA development

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A1020B equivalent
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RadTolerant FPGAs
RadTolerant Architecture
The Actel architecture is composed of fine-grained logic
modules that produce fast, efficient logic designs. All devices
are composed of logic modules, routing resources, clock
networks, and I/O modules which are the building blocks for
fast logic designs.
Logic Modules
These RadTolerant devices contain two types of logic
modules, combinatorial (C-modules) and sequential
(S-modules). RT1020 and A1020B devices contain only
C-modules.
The C-module, shown in Figure 1, implements the following
function:
Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
where:
S0=A0*B0
S1=A1+B1
The S-module, shown in Figure 2, is designed to implement
high-speed sequential functions within a single logic module.
The S-module implements the same combinatorial logic
function as the C-module while adding a sequential element.
The sequential element can be configured as either a D-type
A0
B0
A1
B1
S0
D00
D00
D10
D11
S1
Y
Figure 1 • C-Module Implementation
flip-flop or a transparent latch. To increase flexibility, the
S-module register can be by-passed so it implements purely
combinatorial logic.
Flip-flops can also be created using two C-modules. The SEU
characteristics differ between an S-module flip-flop and a
flip-flop created using two C-modules. For details see the
Design Techniques for RadHard Field Programmable Gate
Arrays application note at http://www.actel.com/hirel.
D00
D01
YD
Q OUT
D10
D11 S0
S1
CLR
D00
D01
YD
Q OUT
D10
D11 S0 GATE
S1
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D0
mD1
.coS
Y
DQ
GATE
CLR
OUT
heet4UUp to 4-Input Function Plus Latch with Clear
www.DataSFigure 2 • S-Module Implementation
Up to 7-Input Function Plus Latch
D00
D01 Y OUT
D10
D11 S0
S1
Up to 8-Input Function (Same as C-Module)
5

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A1020B diode, scr
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RadTolerant FPGAs
Actel Extended Flow1
Step Screen
Method
Requirement
1. Wafer Lot Acceptance2
2. Destructive In-Line Bond Pull3
5007 with Step Coverage Waiver
2011, Condition D
All Lots
Sample
3. Internal Visual
2010, Condition A
100%
4. Serialization
100%
5. Temperature Cycling
1010, Condition C
100%
6. Constant Acceleration
7. Particle Impact Noise Detection
2001, Condition D or E, Y1 Orientation Only
2020, Condition A
100%
100%
8. Radiographic
2012
100%
9. Pre-Burn-In Test
In accordance with applicable Actel device specification
100%
10. Burn-in Test
1015, Condition D, 240 hours @ 125°C minimum
100%
11. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification
100%
12. Reverse Bias Burn-In
1015, Condition C, 72 hours @ 150°C minimum
100%
13. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification
100%
14.
Percent Defective Allowable (PDA)
Calculation
5%, 3% Functional Parameters @ 25°C
All Lots
15. Final Electrical Test
a. Static Tests
(1) 25°C
(Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table 15)
(2) –55°C and +125°C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
In accordance with Actel applicable device specification,
which includes a, b, and c:
5005
5005
5005
5005
5005
100%
100%
100%
100%
16. Seal
a. Fine
b. Gross
1014
100%
17. External Visual
2009
100%
Notes:
1. Actel offers the extended flow for customers that require additional screening beyond the requirements of MIL-STD-883, Class B. Actel is
compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow
incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883 Class S. The exceptions to Method 5004 are
mshown in notes 2 and 3 below.
o2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived.
.c3. Method 5004 requires a 100 percent, non-destructive bond pull (Method 2023). Actel substitutes a destructive bond pull (Method 2011),
Condition D on a sample basis only.
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A1020B transistor, igbt
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RadTolerant FPGAs
RT1020, A1020B Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
Global Clock Network
tCKH
Input Low to High
FO = 16
FO = 128
6.0
6.9 ns
tCKL Input High to Low
FO = 16
FO = 128
7.9
8.7 ns
tPWH
Minimum Pulse Width High
FO = 16
FO = 128
8.0
8.4
ns
tPWL
Minimum Pulse Width Low
FO = 16
FO = 128
1.5
2.2
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
1.5
2.3 ns
tP Minimum Period
FO = 16
FO = 128
16.3
17.5
ns
fMAX
Maximum Frequency
TTL Output Module Timing1
FO = 16
FO = 128
60
50 MHz
tDLH Data to Pad High
tDHL Data to Pad Low
tENZH
Enable Pad Z to High
tENZL
Enable Pad Z to Low
tENHZ
Enable Pad High to Z
tENLZ
Enable Pad Low to Z
dTLH
Delta Low to High
dTHL
Delta High to Low
CMOS Output Module Timing1
8.3 ns
9.3 ns
8.1 ns
9.8 ns
12.3 ns
11.1 ns
0.07 ns/pF
0.10 ns/pF
tDLH Data to Pad High
9.8 ns
tDHL Data to Pad Low
7.9 ns
tENZH
Enable Pad Z to High
7.4 ns
tENZL
Enable Pad Z to Low
10.2 ns
tENHZ
Enable Pad High to Z
12.3 ns
tENLZ
Enable Pad Low to Z
11.1 ns
mdTLH
Delta Low to High
0.13 ns/pF
.codTHL
Delta High to Low
0.07 ns/pF
UNotes:
t41. Delays based on 35 pF loading.
e2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
ehttp://www.actel.com/appnotes.
www.DataSh 21

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