HN29V2G74WT-30 Datasheet PDF - Renesas Technology
Part Number | HN29V2G74WT-30 | |
Description | AG-AND Flash Memory | |
Manufacturers | Renesas Technology | |
Logo | ||
There is a preview and HN29V2G74WT-30 download ( pdf file ) link at the bottom of this page. Total 70 Pages |
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(128M × 8-bit) ×2 AG-AND Flash Memory
REJ03C0182-0200Z
Rev. 2.00
Jul.21.2004
Description
The HN29V2G74 is a 2G-bit AG-AND flash memory. It mounts two 1G-bit AG-AND flash memories
with multi-level memory cells, which are programmable and erasable automatically with a single 3.0 V
power supply. It achieves a write speed of 10 Mbytes/sec, which is 5 times faster than Renesas's previous
multi level cell Flash memory, using 0.13µm process technology and AG-AND (Assist Gate-AND) type
Flash memory cell using multi level cell technology provides both the most cost effective solution and high
speed programming.
Features
• On-board single power supply: VCC = 2.7 V to 3.6 V
• Operation Temperature range: Ta = 0 to +70°C
• Memory organization
Memory array: (2048+64) bytes × 16384 page × 4 Bank × 2
Page size: (2048+64) bytes × 2
Block size: (2048+64) bytes × 2 page × 2
Page Register: (2048+64) bytes × 4 Bank × 2
• Multi level memory cell
2bit/cell
• Automatic program
Page program
Multi bank program
Cache program
2 page cache program
• Automatic Erase
Block Erase
Multi Bank Block Erase
• Access time
Memory array to register (1st access time): 120 µs max
Serial access: 35 ns min
Rev.2.00, Jul.21.2004, page 1 of 91
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HN29V2G74WT-30
Block Diagram
Left side chip
Page address buffer
16
Bank0
Bank Bank
12
Bank3
X-
decoder
Memory array
(2048+64)
x 16384 page
16
I/O1_1
to
I/O8_1
VCC1
VSS1
Multi-
plexer
8 Data
input
buffer
8
Data register
2048+64 byte
Y-Gating
Y-Decoder
Input data
control
8 12
Column address
counter
R/B1
CE1
RE1
WE1
WP1
CLE1
ALE1
PRE1
RES1
Control
signal
buffer
Read/Program/Erase
control
X-
decoder
Memory array
(2048+64)
x 16384 page
Data register
2048+64 byte
Y-Gating
Y-Decoder
Data
output buffer
Right side chip
Page address buffer
16
Bank0
Bank Bank
12
Bank3
X-
decoder
Memory array
(2048+64)
x 16384 page
16
I/O1_2
to
I/O8_2
VCC2
VSS2
Multi-
plexer
8 Data
input
buffer
8
Data register
2048+64 byte
Y-Gating
Y-Decoder
Input data
control
8 12
Column address
counter
R/B2
CE2
RE2
WE2
WP2
CLE2
ALE2
PRE2
RES2
Control
signal
buffer
Read/Program/Erase
control
X-
decoder
Memory array
(2048+64)
x 16384 page
Data register
2048+64 byte
Y-Gating
Y-Decoder
Data
output buffer
Rev.2.00, Jul. 21.2004, page 5 of 91
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for HN29V2G74WT-30 electronic component. |
Information | Total 70 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ HN29V2G74WT-30.PDF Datasheet ] |
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