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PDF ISL6316 Data sheet ( Hoja de datos )
| Número de pieza | ISL6316 | |
| Descripción | Enhanced 4-Phase PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
ISL6316
Data Sheet
August 31, 2005
FN9227.0
Enhanced 4-Phase PWM Controller with
6-Bit VID Code Capable of Precision
RDS(ON) or DCR Differential Current
Sensing for VR10 Application
The ISL6316 controls microprocessor core voltage regulation
by driving up to 4 synchronous-rectified buck channels in
parallel. Multiphase buck converter architecture uses
interleaved timing to multiply channel ripple frequency and
reduce input and output ripple currents. Lower ripple results in
fewer components, lower component cost, reduced power
dissipation, and smaller implementation area.
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6316 features a high
bandwidth control loop and ripple frequencies up to >4MHz to
provide optimal response to the transients.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6316
senses current by utilizing patented techniques to measure
the voltage across the on resistance, RDS(ON), of the lower
MOSFETs or DCR of the output inductor during the lower
MOSFET conduction intervals. Current sensing provides the
needed signals for precision droop, channel-current
balancing, and over-current protection. A programmable
internal temperature compensation function is implemented to
effectively compensate for the temperature coefficient of the
current sense element.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote and
local grounds can be completely eliminated using the remote-
sense amplifier. Eliminating ground differences improves
regulation and protection accuracy. The threshold-sensitive
enable input is available to accurately coordinate the start up
of the ISL6316 with any other voltage rail. Dynamic-VID™
technology allows seamless on-the-fly VID changes. The
offset pin allows accurate voltage offset settings that are
independent of VID setting.
Ordering Information
TEMP.
PART NUMBER (°C)
PACKAGE
PKG.
DWG. #
ISL6316CRZ (Note) 0 to 70 40 Ld 6x6 QFN (Pb-free) L40.6x6
ISL6316IRZ (Note) -40 to 85 40 Ld 6x6 QFN (Pb-free) L40.6x6
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
twinitwhplbawotethwteSr.mnDPinbaaatitonand fPSinbih-sfhree, eweshtoic4ldheUarrine.gcRooopHmeSractioomnsp.liIanntetrasnildPcbo-fmrepeatible
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Precision Multiphase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Precision Reference-Voltage Offset
• Precision RDS(on) or DCR Current Sensing
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology
- 6-Bit VID Code at 12.5mV per Bit
- 0.8375V to 1.600V Operation Range
• Thermal Monitoring
• Programmable Temperature Compensation
• Threshold-Sensitive Enable Pins to Enable VR and
Ensure Power Sequencing Control
• Overcurrent Protection
• Overvoltage Protection
• 2, 3 or 4 Phase Operation
• Adjustable Switching Frequency up to 1MHz per Phase
• Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Dynamic VID™ is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
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ISL6316
Typical Application - 4-Phase Buck Converter with RDS(ON) Sensing and Integrated TCOMP
+12V
VCC
BOOT
VIN
UGATE
PVCC
PHASE
PWM
ISL6612
DRIVER
LGATE
+5V GND
VTT
PGOOD
VID5
VID4
VID3
VID2
VID1
VID0
FB COMP REF
IDROOP
VDIFF
DAC
VSEN
RGND
VCC
EN_VTT
ISL6316
ISEN1+
ISEN1-
PWM1
PWM2
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
PWM4
ISEN4+
ISEN4-
VR_FAN
GND
VR_HOT
TM EN_PWR
+5V TCOMP OFS FS SS
+5V
ROFS RF
RS
NTC
+12V
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+12V
VCC
BOOT
PVCC
PWM
ISL6612
DRIVER
UGATE
PHASE
LGATE
GND
VIN
+12V
VCC
PVCC
BOOT
UGATE
PHASE
PWM
ISL6612
DRIVER
LGATE
GND
VIN
+12V
VCC
BOOT
PVCC
PWM
ISL6612
DRIVER
UGATE
PHASE
LGATE
GND
VIN
µP
LOAD
5 FN9227.0
August 31, 2005
5 Page 
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ISL6316
by the state of PWM3 and PWM4. Tie PWM3 to VCC to
configure for 2-phase operation. Tie PWM4 to VCC to
configure for 3-phase operation.
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
ISEN4+, ISEN4- - The ISEN+ and ISEN- pins are current
sense inputs to individual differential amplifiers. The sensed
current is used for channel current balancing, over current
protection, and droop regulation. Inactive channels should
have their respective current sense inputs left open (for
example, open ISEN4+ and ISEN4- for 3-phase operation).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN.
The voltage across the sense capacitor is proportional to the
inductor current. Therefore, the sense current is proportional
to the inductor current, and scaled by the DCR of the inductor
and RISEN.
When configured for RDS(ON) current sensing, the ISEN1-,
ISEN2-, ISEN3-, and ISEN4- pins are grounded at the lower
MOSFET sources. The ISEN1+, ISEN2+, ISEN3+, and
ISEN4+ pins are then held at a virtual ground. Therefore, a
resistor, connected between these current sense pins and the
drain terminals of the associated lower MOSFET, will carry the
current proportional to the current flowing through that
channel. The sensed current is determined by the negative
voltage across the lower MOSFET when it is ON, which is the
channel current scaled by RDS(ON) and RISEN.
PGOOD - PGOOD indicates that the soft-start is completed
and the output voltage is within the regulated range around
VID setting. It is an open-drain logic output. When OCP or
OVP occurs, PGOOD will be pulled to low. It will also be
pulled low if the output voltage is below the undervoltage
threshold.
OFS - The OFS pin provides a means to program a DC offset
current for generating a DC offset voltage at the REF input.
The offset current is generated via an external resistor and
precision internal voltage references. The polarity of the offset
is selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unterminated.
TCOMP - Temperature compensation scaling input. The
voltage sensed on the TM pin is utilized as the temperature
input to adjust ldroop and the over current protection limit to
effectively compensate for the temperature coefficient of the
current sense element. To implement the integrated
temperature compensation, a resistor divider circuit is needed
with one resistor being connected from TCOMP to VCC of the
controller and another resistor being connected from TCOMP
to GND. Changing the ratio of the resistor values will set the
gain of the integrated thermal compensation. When integrated
temperature compensation function is not used, connect
TCwOwMPwto.DGaNtDa. Sheet4U.com
IDROOP - IDROOP is the output pin of sensed average
channel current which is proportional to load current. In the
application which does not require loadline, leave this pin
open. In the application which requires load line, connect this
pin to FB so that the sensed average current will flow through
the resistor between FB and VDIFF to create a voltage drop
which is proportional to load current.
TM - TM is an input pin for VR temperature measurement.
Connect this pin through NTC themistor to GND and a resistor
to Vcc of the controller. The voltage at this pin is reverse
proportional to VR temperature. ISL6316 monitors the VR
temperature based on the voltage at TM pin and outputs
VR_HOT and VR_FAN signals.
VR_HOT - VR_HOT is used as an indication of high VR
temperature. It is an open-drain logic output. It will be open
when the measured VR temperature reaches certain level.
VR_FAN - VR_FAN is an output pin with open-drain logic
output. It will be open when the measured VR temperature
reaches certain level.
Operation
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multiphase power conversion are
impossible to ignore. The technical challenges associated
with producing a single-phase converter which is both cost-
effective and thermally viable have forced a change to the
cost-saving approach of multiphase. The ISL6316 controller
helps reduce the complexity of implementation by integrating
vital functions and requiring minimal output components. The
block diagrams on pages 4, 5, 6 and 7 provide top level views
of multiphase power conversion using the ISL6316 controller.
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-to-
peak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
11 FN9227.0
August 31, 2005
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ISL6316.PDF ] | |
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