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What is GVT71256D36?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "(GVT7xxxx) 256K x 36 / 512K x 18 Pipelined SRAM".


GVT71256D36 Datasheet PDF - Cypress Semiconductor

Part Number GVT71256D36
Description (GVT7xxxx) 256K x 36 / 512K x 18 Pipelined SRAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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( DataSheet : www.DataSheet4U.com )
1CY7C1329
PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
256K x 36/512K x 18 Pipelined SRAM
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225, 200, 166, and 150 MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA package version and two chip
enables for B and T package versions
• Address pipeline capability
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1360A/GVT71256D36 and CY7C1362A/
GVT71512D18 SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a posi-
tive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), burst control inputs (ADSC, ADSP, and ADV), Write En-
ables (BWa, BWb, BWc, BWd, and BWE), and global write
(GW). However, the CE2 chip enable input is only available for
the TA package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B and T package versions, four pins are used to imple-
ment JTAG test capabilities: Test Mode Select (TMS), Test Da-
ta-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation. The TA package version
does not offer the JTAG capability.
The CY7C1360A/GVT71256D36 and CY7C1362A/
GVT71512D18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
7C1360A-225
71256D36-4.4
7C1362A-225
71512D18-4.4
2.5
570
10
7C1360A-200
71256D36-5
7C1362A-200
71512D18-5
3.0
510
10
7C1360A-166
71256D36-6
7C1362A-166
71512D18-6
3.5
425
10
7C1360A-150
71256D36-6.7
7C1362A-150
71512D18-6.7
3.5
380
10
www.DataSheet4U.com
wwwC.yDparteaSshseSete4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 9, 2001

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GVT71256D36 equivalent
PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
256K X 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 3T, 4T, 5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47, 48,
49, 50
92 (T Version)
43 (TA Version)
5L 93
5G 94
3G 95
3L 96
4M 87
4H 88
4K 89
4E 98
2B 97
- (not available for
PBGA)
4F
92 (for TA Version
only)
86
4G 83
4A 84
4B 85
3R 31
7T 64
Name
A0
A1
A
BWa
BWb
BWc
BWd
BWE
GW
CLK
CE
CE2
CE2
OE
ADV
ADSP
ADSC
MODE
ZZ
Type
Input-
Synchronous
Description
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses associ-
ated with A0 and A1, during burst cycle and wait cycle.
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and
HIGH for a READ cycle. BWa controls DQa. BWb con-
trols DQb. BWc controls DQc. BWd controls DQd. Data
I/O are high impedance if either of these inputs are LOW,
conditioned by BWE being LOW.
Input-
Write Enable: This active LOW input gates byte write
Synchronous operations and must meet the set-up and hold times
around the rising edge of CLK.
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit
WRITE to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the
rising edge of CLK.
Input-
Synchronous
Clock: This signal registers the addresses, data, chip
enables, write control, and burst control inputs on its ris-
ing edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
Input-
Chip Enable: This active HIGH input is used to enable
Synchronous the device.
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device. Not available for B and T package versions.
Input
Output Enable: This active LOW asynchronous input en-
ables the data output drivers.
Input-
Address Advance: This active LOW input is used to con-
Synchronous trol the internal burst counter. A HIGH on this pin gener-
ates wait cycle (no address advance).
Input-
Synchronous
Address Status Processor: This active LOW input, along
with CE being LOW, causes a new external address to
be registered and a READ cycle is initiated using the new
address.
Input-
Synchronous
Address Status Controller: This active LOW input caus-
es the device to be deselected or selected along with
new external address to be registered. A READ or
WRITE cycle is initiated depending upon write control
inputs.
Input-
Static
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Input-
Snooze: This active HIGH input puts the device in low
Asynchronous power consumption standby mode. For normal opera-
tion, this input has to be either LOW or NC (No Connect).
5


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Featured Datasheets

Part NumberDescriptionMFRS
GVT71256D36The function is (GVT7xxxx) 256K x 36 / 512K x 18 Pipelined SRAM. Cypress SemiconductorCypress Semiconductor

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