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PDF APA075 Data sheet ( Hoja de datos )
| Número de pieza | APA075 | |
| Descripción | (APAxxx) 2nd Generation Reprogrammable Flash Fpgas | |
| Fabricantes | Actel Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de APA075 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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v3.0
ProASICPLUS Flash Family FPGAs
TM
Features and Benefits
High Capacity
• 75,000 to 1 million System Gates
• 27k to 198kbits of Two-Port SRAM
• 66 to 712 User I/Os
Reprogrammable Flash Technology
• 0.22µ 4LM Flash-based CMOS Process
• Live at Power-Up, Single-Chip Solution
• No Configuration Device Required
• Retains Programmed Design during Power-Down/
Power-Up Cycles
Performance
• 3.3V, 32-bit PCI (up to 50 MHz)
• Two Integrated PLLs
• External System Performance up to 150 MHz
Secure Programming
• The Industry’s Most Effective Security Key (FlashLock)
Prevents Read Back of Programming Bitstream
Low Power
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
• Small, Efficient, Configurable (Combinatorial or
Sequential) Logic Cells
High Performance Routing Hierarchy
• Ultra-Fast Local and Long-Line Network
• High Speed Very Long-Line Network
• High Performance, Low Skew, Splittable Global Network
ProASICPLUS Product Profile
Device
Maximum System Gates
Maximum Tiles (Registers)
Embedded RAM Bits (k=1,024 bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package (by pin count)
TQFP
PQFP
PBGA
FBGA
APA075
75,000
3,072
27k
12
2
2
4
24
158
Yes
Yes
100, 144
208
144
APA150
150,000
6,144
36k
16
2
2
4
32
242
Yes
Yes
100
208
456
144, 256
• 100% Routability and Utilization
I/O
• Schmitt-Trigger Option on Every Input
• Mixed 2.5V/3.3V Support with Individually-Selectable
Voltage and Slew Rate
• Bidirectional Global I/Os
• Compliance with PCI Specification Revision 2.2
• Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
• Pin Compatible Packages across ProASICPLUS Family
Unique Clock Conditioning Circuitry
• PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
• Internal and/or External Dynamic PLL Configuration
• Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
• Flexibility with Choice of Industry-Standard Frontend
Tools
• Efficient Design through Frontend Timing and Gate
Optimization
ISP Support
• In-System Programming (ISP) via JTAG Port
SRAMs and FIFOs
• ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
• 24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
APA300
300,000
8,192
72k
32
2
2
4
32
290
Yes
Yes
APA450
450,000
12,288
108k
48
2
2
4
48
344
Yes
Yes
APA600
600,000
21,504
126k
56
2
2
4
56
454
Yes
Yes
APA750
750,000
32,768
144k
64
2
2
4
64
562
Yes
Yes
APA1000
1,000,000
56,320
198k
88
2
2
4
88
712
Yes
Yes
208 208
208 20w8ww.DataS2h0e8et4U.com
456 456
456 456 456
144, 256 144, 256, 484 256, 484, 676 676, 896 896, 1152
www.DataSheet4U.com
May 2003
© 2003 Actel Corporation
www.DataSheet4U.com
1
*See Actel’s website for the latest version of the datasheet.
1 page  
ProASICPLUS Flash Family FPGAs
ProASICPLUS Architecture
The proprietary ProASICPLUS architecture provides
granularity comparable to gate arrays.
The ProASICPLUS device core consists of a Sea-of-Tiles™
(Figure 1). Each tile can be configured as a 3-input logic
function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming the appropriate Flash switch
interconnections (Figure 2 on page 6 and Figure 3 on
page 6). Tiles and larger functions are connected with any
of the four levels of routing hierarchy. Flash switches are
distributed throughout the device to provide nonvolatile,
reconfigurable interconnect programming. Flash switches
are programmed to connect signal lines to the appropriate
logic cell inputs and outputs. Dedicated high-performance
lines are connected as needed for fast, low-skew global
signal distribution throughout the core. Maximum core
utilization is possible for virtually any design.
ProASICPLUS devices also contain embedded two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming options include synchronous or asynchronous
operation, two-port RAM configurations, user defined depth
and width, and parity generation or checking. Please see
the “Embedded Memory Configurations” section on page 21
for more information.
Flash Switch
Unlike SRAM FPGAs, ProASICPLUS uses a live on power-up
ISP Flash switch as its programming element.
In the ProASICPLUS Flash switch, two transistors share the
floating gate, which stores the programming information.
One is the sensing transistor, which is only used for writing
and verification of the floating gate voltage. The other is the
switching transistor. It can be used in the architecture to
connect/separate routing nets or to configure logic. It is also
used to erase the floating gate (Figure 2 on page 6).
Logic Tile
The logic tile cell (Figure 3 on page 6) has three inputs (any
or all of which can be inverted) and one output (which can
connect to both ultra-fast local and efficient long-line
routing resources). Any three-input, one-output logic
function (except a three-input XOR) can be configured as
one tile. The tile can be configured as a latch with clear or
set or as a flip-flop with clear or set. Thus, the tiles can
flexibly map logic and sequential gates of a design.
Figure 1 • The ProASICPLUS Device Architecture
RAM Block
256x9 Two-Port SRAM
or FIFO Block
I/Os
Logic Tile
RAM Block
256x9 Two Port SRAM
or FIFO Block
v3.0
5
5 Page 
ProASICPLUS Flash Family FPGAs
Input/Output Blocks
To meet complex system demands, the ProASICPLUS family
offers devices with a large number of user I/O pins, up to
712 on the APA1000. If the I/O pad power supply (VDDP) is
3.3V, each I/O can be selectively configured at the 2.5V and
3.3V threshold levels. Table 3 shows the available supply
voltage configurations (the PLL block uses an independent
2.5V supply on the AVDD and AGND pins). All I/Os include
ESD protection circuits. Each I/O has been tested to 2000V
to the human body model (per JESD22 (HMB)).
Table 3 • ProASICPLUS I/O Power Supply Voltages
2.5V
VDDP
3.3V
Input Compatibility
2.5V
3.3V, 2.5V
Output Drive
Note: VDD is always 2.5V.
2.5V
3.3V, 2.5V
Six or seven standard I/O pads are grouped with a GND pad
and either a VDD (core power) or VDDP (I/O power) pad. Two
reference bias signals circle the chip. One protects the
cascaded output drivers while the other creates a virtual
VDD supply for the I/O ring.
I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an
input, an output, a tristate driver, or a bidirectional buffer
(Figure 9 and Table 4).
3.3V/2.5V
Signal Control
Pull-up
Control
Y
EN
Pad
A
3.3V/2.5V Signal Control Drive
Strength and Slew-Rate Control
Figure 9 • I/O Block Schematic Representation
Table 4 • I/O Features
Function
Description
I/O pads configured as inputs
• Individually selectable 2.5V or 3.3V threshold levels
• Optional pull-up resistor
• Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can
be configured as an input only, not a bidirectional buffer. This input type may be
slower than a standard input under certain conditions and has a typical hysteresis of
0.35V. I/O macros with an “S” in the standard I/O library have added Schmitt
capabilities
I/O pads configured as outputs
• 3.3V PCI Compliant
• Individually selectable 2.5V or 3.3V compliant output signals
– 2.5V – JEDEC JESD 8-5
– 3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)
• 3.3V PCI compliant
• Ability to drive LVTTL and LVCMOS levels
• Selectable drive strengths
• Selectable slew rates
• Tristate
I/O pads configured as bidirectional • Individually selectable 2.5V or 3.3V compliant output signals
buffers
– 2.5V – JEDEC JESD 8-5
– 3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)
• 3.3V PCI compliant
• Optional pull-up resistor
• Selectable drive strengths
• Selectable slew rates
• Tristate
v3.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet APA075.PDF ] | |
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