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STA001 Datasheet PDF - ST Microelectronics

Part Number STA001
Description RF FRONT-END FOR DIGITAL RADIO
Manufacturers ST Microelectronics 
Logo ST Microelectronics Logo 

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STA001
RF FRONT-END FOR DIGITAL RADIO
PRODUCT PREVIEW
s SINGLE CHIP RECEIVER FOR SATELLITE
DIGITAL TRANSMISSION
s SUPERHETERODYNE RECEIVER WITH IF
OUTPUT
s HIGH INPUT INTERCEPT POINT, LOW
MIXER NOISE
ms 54dB IF VGA GAIN RANGE
os ADJUSTABLE RF GAIN
s ADJUSTABLE IF GAIN
.cs INTEGRATED RF VCO
s INTEGRATED IF VCO
Us INTEGRATED SYNTHESIZER
t4s I2CBUS COMPATIBLE PROGRAMMING
INTERFACE
s UNREGULATED 2.7 V TO 3.3V VOLTAGE
eSUPPLY
es LOW COST EXTERNAL COMPONENTS
hDESCRIPTION
SThe STA001 is an RF IC using STMicroelectronics
TQFP 44
ORDERING NUMBER: STA001
HSB2 High Speed Bipolar Technology for one chip so-
lution for the Starman digital satellite radio receiver.
The STA001 is assembled in a TQFP44 package.
The frontend architecture is a double conversion re-
ceiver (see block diagram) .
The chip includes all the RF functions up to low IF
and manages the signals to and from the baseband.
taBLOCK DIAGRAM
PADJ1, PADJ2
aVDD1
.DVSS1
wLNI, NLNI
SUPPLY1 :RF
LNA
CE
RF MIXER
AGC1, AGC2
SIP, SIN SOP, SON
GADJ1, GADJ2
IF1 to IF2 MIXER
SUPPLY4 :IF1,
IF2 &PLL2
VDD4
VSS4
IF2 BUFFER
RXI, NRXI
IF1 BUFFER
V GA
1.8366 Mhz
FLT2
wFLT1
1338.14 - 1375.4 MHz
117.0806 MHz
TK2, NTK2
TK 1,
wNTK1
1st PLL
omENRFOSC
U.cTLCK
LOCK
DETECTOR
VCO
CHARGE
PUMP
PHASE
D ETECTOR
:363.625- 373.75
t4VDD2
SheeVSS2
SUPPLY2 :PLL1 +
Crystal osc .
I2CBUS INTERFACE
CHANNEL SELECTION
SDA SCL
113.23KHz
3.68MHz
PHASE
DETECTOR
CH ARGE
PUMP
VCO
: 1034
DIFFERENTIAL
SINGLE ENDED
:130 2nd PLL
:4
BUFFER
14.72MHz
M_CLK
MUX
OSC
SUPPLY3 :DIG.
VDD3
VSS3
XTAL1, XT AL2
XOSEL REF
ataNovember 2002
www.DThis is preliminary information on a new product now in development. Details are subject to change without notice.
1/20

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STA001 equivalent
STA001
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Test Conditi on
GVtrim Minimum Voltage Gain
Input LNI, NLNI pins; output SIP, NIP pins.
RL = 200Ω, Rext=0
Zi Input impedance R || C Balanced, LNI, NLNI pins
Zo Output impedance
Balanced, SIP, SIN pins
Rl Input Return Loss
LNI, NLNI pins
IIP3 Input IP3
Input LNI, NLNI pins; output SIP, NIP pins,
Rl=200Ω, PADJ1, PADJ2 floating
IIP3trim Input IP3 minimum gain Input LNI, NLNI pins; output SIP, NIP pins,
Rl=200Ω, Rext=0 on PADJ1, PADJ2
1dBcp Input 1 dB compression Input LNI, NLNI pins; output SIP, NIP pins,
point
Rl=200Ω, PADJ1, PADJ2 floating
1dBcptri Input 1 dB compression Input LNI, NLNI pins; output SIP, NIP pins,
m point
Rl=200Ω, PADJ1, PADJ2 Rext=0 on PADJ1,
PADJ2
NF
NFtrim
Noise figure contribution Measurement conditions: Input LNI, NLNI
pins; output SIP, NIP pins. Rs=50Ω,
Rl=200Ω, DSB, PADJ1, PADJ2 floating
Noise figure contribution Measurement conditions: Input LNI, NLNI
minimum gain
pins; output SIP, NIP pins. Rs=50Ω,
Rl=200Ω, DSB, Rext=0 on PADJ1, PADJ2
IF1leak LO1 to IF1 leakage
RFleak LO1 to RF leakage
VDC LNI, NLNI common mode AC coupled to the Balun
DC voltage
VDC SIP, SIN common mode AC coupled to the SAW filter
DC voltage
Min.
22
-20
-19.5
-100
-100
VDD-
1.2
VDD-
1.3
Typ.
25
75
0.2
50
14
-26
-24
5
6.5
VDD-1
VDD-
1.1
Max.
28
-15
-11.5
-25
-30
VDD-
0.8
VDD-
0.9
Unit
dB
pF
dB
dBm
dBm
dBm
dBm
dB
dB
dBm
dBm
V
V
IF VGA AMPLIFIER, IF MIXER AND OUTPUT BUFFER (T = 25°, VDD-VSS = 3V)
BWi Input signal BW
114
BWo Output signal BW
0.6
Gmin Minimum gain
Input LNI, NLNI pins; output SIP, NIP pins.
Rl=high impedance V(AGC1,2)=0V
Gmax Maximum gain
Input LNI, NLNI pins; output SIP, NIP pins.
Rl=high impedance V(AGC1,2)=3V
71
IAGC Input current in AGC
control pin
ZAGC AGC pin input
impedance
116.5 MHz
3.1 MHz
32 37 dB
86 dB
10 µA
600 K
5/20


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