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PDF QD17EL07 Data sheet ( Hoja de datos )
| Número de pieza | QD17EL07 | |
| Descripción | TFT LCD Module | |
| Fabricantes | Quanta_Display | |
| Logotipo |  |
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Quanta Display Inc
Preliminary
Quanta Display Inc.
SPECIFICATION
QD17EL0711 Page 1/21
Doc No. QD17EL0711
Doc. REV.: 00
Issue Date:03/24/2005
With RoHS
compliant
Specification for TFT LCD Module
Model No.
QD17EL07 Rev.:11
? Approved By
Quanta Display Inc.
1 page  
Quanta Display Inc
4. Input Terminals
4-1. TFT-LCD panel driving
CN1 (LVDS signals and +5V DC power supply)
Using connector: AL2307-A0G1D-P(PII)
Corresponding connector: FI-X30M or FI-X30H (JAE)
Interface Cable Pin Assignments
Pin No.
Symbol
Function
QD17EL0711 Page 5/21
Remark
1 R1IN0- Receiver signal of Odd side pixels (-)
2 R1IN0+ Receiver signal of Odd side pixels (+)
3 R1IN1- Receiver signal of Odd side pixels (-)
4 R1IN1+ Receiver signal of Odd side pixels (+)
5 R1IN2- Receiver signal of Odd side pixels (-)
6 R1IN2+ Receiver signal of Odd side pixels (+)
7 GND
8 CK1IN- Clock signal of Odd side pixels (-)
9 CK1IN+ Clock signal of Odd side pixels (+)
10 R1IN3- Receiver signal of Odd side pixels (-)
11 R1IN3+ Receiver signal of Odd side pixels (+)
12 R2IN0- Receiver signal of Even side pixels (-)
13 R2IN0+ Receiver signal of Even side pixels (+)
14 GND
15 R2IN1- Receiver signal of Even side pixels (-)
16 R2IN1+ Receiver signal of Even side pixels (+)
17 GND
18 R2IN2- Receiver signal of Even side pixels (-)
19 R2IN2+ Receiver signal of Even side pixels (+)
20 CK2IN- Clock signal of Even side pixels (-)
21 CK2IN+ Clock signal of Even side pixels (+)
22 R2IN3- Receiver signal of Even side pixels (-)
23 R2IN3+ Receiver signal of Even side pixels (+)
24 GND
25 GND
26 NC
27 GND
28 VDD +5V power supply
29 VDD +5V power supply
30 VDD +5V power supply
? Note 1? All GND(ground) pins should be connected together.
? Note 2? All VDD (power supply) pins should be connected together.
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Power
Power
Power
5 Page 
Quanta Display Inc
installed in your instrument.
7. Timing characteristics of LCD module input signals
7-1. Timing characteristics
(This is specified at digital outputs of LVDS driver.)
QD17EL0711 Page 11/21
DE MODE:
Item
Description Condition Min.
Typ.
Max.
Unit
Frame
Line
V total line
number
Data
daration
H total
pixel
number
Data
duration
-
-
-
-
1029
-
1066
1024
1600
H
-H
672
844
1400
CLK
- 640
- CLK
( Clock)
Item
Min.
Typ.
Max. Unit Remark
Frequency
40 54 67.5 MHz
Note)1. Typ. Timing is 1280X1024@64KHz/60Hz SXGA
3. If increase Vsync cycle too much, it may cause flicker.
11 Page | ||
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| PDF Descargar | [ Datasheet QD17EL07.PDF ] | |
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