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PDF MC74HC157A Data sheet ( Hoja de datos )

Número de pieza MC74HC157A
Descripción Quad 2-Input Data Selectors / Multiplexers
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo




1. MC74HC157A






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No Preview Available ! MC74HC157A Hoja de datos, Descripción, Manual

MQSeuClae7dc4tH2oS−ChrIs1ene5p/t7u4MUAtu.DclotaimptalexersHigh−Performance Silicon−Gate CMOS
ataThe MC74HC157A is identical in pinout to the LS157. The device
.Dinputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
wThis device routes 2 nibbles (A or B) to a single port (Y) as
wdetermined by the Select input. The data is presented at the outputs in
w noninverted form. A high level on the Output Enable input sets all four
mY outputs to a low level.
oFeatures
.cOutput Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
ULow Input Current: 1.0 mA
t4High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
eNo. 7A
Chip Complexity: 82 FETs or 20.5 Equivalent Gates
.DataShePb−Free Packages are Available*
16
1
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC157AN
AWLYYWWG
1
16
1
16
1
16
SOIC−16
D SUFFIX
CASE 751B
HC157AG
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HC
157A
ALYWG
G
1
16
1
SOEIAJ−16
F SUFFIX
CASE 966
16
74HC157A
ALYWG
1
w A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
w W, WW = Work Week
G = Pb−Free Package
w mG = Pb−Free Package
o(Note: Microdot may be in either location)
t4U.cORDERING INFORMATION
eSee detailed ordering and shipping information in the package
edimensions section on page 2 of this data sheet.
ataSh*For additional information on our Pb−Free strategy and soldering details, please
.Ddownload the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ww© Semiconductor Components Industries, LLC, 2005
wJune, 2005 − Rev. 9
1
Publication Order Number:
MC74HC157A/D

1 page




MC74HC157A pdf
MC74HC157A
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is
transferred to the outputs when the Select input is at a low
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
Nibble B inputs. The data present on these pins is
transferred to the outputs when the Select input is at a high
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.
The data present on these pins is in its noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
SWITCHING WAVEFORMS
tr
INPUT A OR B
tPLH
OUTPUT Y
90%
50%
10%
90%
50%
10%
tTLH
tf
VCC
GND
tPHL
tTHL
tr
SELECT
tPLH
90%
50%
10%
OUTPUT Y
90%
50%
10%
tTLH
tf
VCC
GND
tPHL
tTHL
Figure 3. HC157A
Figure 4. Y versus Selected, Noninverted
tr
OUTPUT
ENABLE
tPHL
OUTPUT Y
90%
50%
10%
90%
50%
10%
tTHL
Figure 5. HC157A
tf
VCC
GND
tPLH
tTLH
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 6. Test Circuit
http://onsemi.com
5

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